hal_gpio_v150_regs_op.h

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#ifndef HAL_GPIO_V150_REGS_OP_H
#define HAL_GPIO_V150_REGS_OP_H
 
#include <stdint.h>
#include "common_def.h"
#include "hal_gpio_v150_regs_def.h"
#include "gpio_porting.h"
 
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
 
#define hal_gpio_set_bit(x, y, z) (((uint32_t)(x) & ~bit(y)) | (((uint32_t)(z) & 1U) << (uint32_t)(y)))
 
#define hal_gpio_toggle_bit(x, y) (((x) & ~bit(y)) | ((~(x)) & bit(y)))
 
#define hal_gpio_read_bit(x, y) (((uint32_t)(x) >> (uint32_t)(y)) & 1U)
 
extern uintptr_t g_gpios_regs[GPIO_CHANNEL_MAX_NUM];
 
static inline gpio_v150_regs_t *gpios_v150_regs(uint32_t channel)
{
    return (gpio_v150_regs_t *)g_gpios_regs[channel];
}
 
static inline void hal_gpio_gpio_sw_out_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_out =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_out, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_sw_out_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_out, group_pin);
}
 
static inline void hal_gpio_gpio_sw_out_toggle_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_out =
        hal_gpio_toggle_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_out, group_pin);
}
 
static inline uint32_t hal_gpio_gpio_sw_oen_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_oen, group_pin);
}
 
static inline void hal_gpio_gpio_sw_oen_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_oen =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_oen, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_sw_ctl_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_ctl, group_pin);
}
 
static inline void hal_gpio_gpio_sw_ctl_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_ctl =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_sw_ctl, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_int_en_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_en, group_pin);
}
 
static inline void hal_gpio_gpio_int_en_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_en =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_en, group_pin, val);
}
 
static inline void hal_gpio_gpio_int_en_disable_all(uint32_t channel, uint32_t group)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_en = 0x0;
}
 
static inline uint32_t hal_gpio_gpio_int_mask_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_mask, group_pin);
}
 
static inline void hal_gpio_gpio_int_mask_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_mask =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_mask, group_pin, val);
}
 
static inline void hal_gpio_gpio_int_mask_unmask_all(uint32_t channel, uint32_t group)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_mask = 0x0;
}
 
static inline void hal_gpio_gpio_int_mask_mask_all(uint32_t channel, uint32_t group)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_mask = 0xFFFFFFFF;
}
 
static inline uint32_t hal_gpio_gpio_int_type_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_type, group_pin);
}
 
static inline void hal_gpio_gpio_int_type_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_type =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_type, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_int_polarity_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_polarity, group_pin);
}
 
static inline void hal_gpio_v150_gpio_int_polarity_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin,
                                                           uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_polarity =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_polarity, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_int_dedge_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_dedge, group_pin);
}
 
static inline void hal_gpio_gpio_int_dedge_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_dedge =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_dedge, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_int_debounce_get_bit(uint32_t channel, uint32_t group, uint32_t group_pin)
{
    return hal_gpio_read_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_debounce, group_pin);
}
 
static inline void hal_gpio_gpio_int_debounce_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin,
                                                      uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_debounce =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_debounce, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_int_raw_get_data(uint32_t channel, uint32_t group)
{
    return gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_raw;
}
 
static inline uint32_t hal_gpio_gpio_intr_get_data(uint32_t channel, uint32_t group)
{
    return gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_intr;
}
 
static inline void hal_gpio_gpio_int_eoi_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_eoi =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_eoi, group_pin, val);
}
 
static inline void hal_gpio_gpio_int_eoi_clr_all(uint32_t channel, uint32_t group)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_eoi = 0xFFFFFFFF;
}
 
static inline void hal_gpio_gpio_data_set_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_data_set =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_data_set, group_pin, val);
}
 
static inline void hal_gpio_gpio_data_clr_set_bit(uint32_t channel, uint32_t group, uint32_t group_pin, uint32_t val)
{
    gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_data_clr =
        hal_gpio_set_bit(gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_data_clr, group_pin, val);
}
 
static inline uint32_t hal_gpio_gpio_get_int_en(uint32_t channel, uint32_t group)
{
    return gpios_v150_regs(channel)->gpio_group_cfg[group].gpio_int_en;
}
 
void hal_gpio_v150_intr_rebase(uint32_t channel, uint32_t group);
 
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
 
#endif