hal_uart_v151_regs_op.h

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/*
 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2023-2023. All rights reserved.
 * Description:  UART HAL Header.
 *
 * Create:  2023-02-17
 */
 
#ifndef HAL_UART_V151_REGS_OP_H
#define HAL_UART_V151_REGS_OP_H
 
#include "platform_core.h"
#include "hal_uart_v151_regs_def.h"
#include "hal_uart.h"
 
#define HAL_UART_ENABLE_FLAG_NONE 0
#define HAL_UART_ENABLE_FLAG_RX   (1U << 0)
#define HAL_UART_ENABLE_FLAG_TX   (1U << 1)
#define HAL_UART_ENABLE_FLAG_CTS  (1U << 2)
#define HAL_UART_ENABLE_FLAG_RTS  (1U << 3)
 
extern uart_reg_t* g_hal_uart_reg[UART_BUS_MAX_NUMBER];
 
typedef enum {
    HAL_UART_FIFO_DISABLED,
    HAL_UART_FIFO_ENABLED,
} hal_uart_fifo_t;
 
typedef enum {
    HAL_UART_PTIM_MODE_DISABLED,
    HAL_UART_PTIM_MODE_ENABLED,
} hal_uart_ptim_mode_t;
 
typedef enum {
    HAL_UART_AUTO_FLOW_CTL_DISABLED,
    HAL_UART_AUTO_FLOW_CTL_ENABLED,
} hal_uart_auto_flow_ctl_t;
 
typedef enum {
    HAL_UART_SAMPLE_BAUD_RATE_EIGHT = 0x7,
    HAL_UART_SAMPLE_BAUD_RATE_SIXTEEN = 0xf,
} hal_uart_sample_baud_rate_t;
 
typedef enum {
    HAL_UART_LOW_POWER_REQ_DISABLED,
    HAL_UART_LOW_POWER_REQ_ENABLED,
} hal_uart_low_power_req_t;
 
// uart dma config
typedef enum {
    HAL_UART_DMA_DISABLE = 0,    // diable tx and rx
    HAL_UART_DMA_RX_EN = 1,      // enable rx
    HAL_UART_DMA_TX_EN = 2,      // enable tx
    HAL_UART_DMA_RX_DISABLE = 3, // diable rx
    HAL_UART_DMA_TX_DISABLE = 4, // diable tx
} hal_uart_dma_config_t;
 
 
typedef enum {
    HAL_UART_INTERRUPT_MODEM_STATUS = 0x0,
    HAL_UART_INTERRUPT_NO_INTERRUPT = 0x1,
    HAL_UART_INTERRUPT_TX = 0x2,
    HAL_UART_INTERRUPT_RX = 0x4,
    HAL_UART_INTERRUPT_RECEIVER_LINE_STATUS = 0x6,
    HAL_UART_INTERRUPT_BUSY_DETECT = 0x7,
    HAL_UART_INTERRUPT_CHAR_TIMEOUT = 0xC,
    HAL_UART_INTERRUPT_ERROR,
    HAL_UART_INTERRUPT_IDLE
} hal_uart_interrupt_t;
 
typedef enum {
    HAL_UART_RX_FIFO_ERR = 0x1,
    HAL_UART_FRAME_ERR = 0x2,
    HAL_UART_PARITY_ERR = 0x4,
    HAL_UART_OVERRUN_ERR = 0x8,
    HAL_UART_BREAK_INTR = 0x10,
} hal_uart_line_error_interrupt_t;
 
/* Uart stop bits modes available */
typedef enum {
    UART_STOP_BITS_1 = 0, /* !< 1 Stop bit */
    UART_STOP_BITS_2 = 1, /* !< 2 Stop bits */
} uart_stop_bits_t;
 
typedef enum {
    UART_ERR_INFO_UARTLCR_H = 0,
    UART_ERR_INFO_UARTCR = 1,
    UART_ERR_INFO_UARTIBRD = 2,
    UART_ERR_INFO_UARTFBRD = 3,
    UART_ERR_INFO_UARTDMACR = 4,
    UART_ERR_INFO_UARTRSR = 5,
    UART_ERR_INFO_UARTRIS = 6,
    UART_ERR_INFO_INT_FLAG = 7,
    UART_ERROR_MAX_INFO_NUM /* The number of uart frame or parity error information */
} uart_err_info_index;
 
#if defined(CONFIG_UART_SUPPORT_DMA)
#define UART_INT_RTI HAL_UART_INTERRUPT_RX
#define UART_INT_RXI HAL_UART_INTERRUPT_CHAR_TIMEOUT
#define UARTIMSC 0
void hal_uart_uartifls_set_rxiflsel(uart_bus_t bus, uint32_t val);
void hal_uart_int_set(uart_bus_t bus, uint32_t reg, uint32_t int_id, uint32_t val);
#endif
 
void hal_uart_set_fifo_en(uart_bus_t uart, hal_uart_fifo_t fifo);
 
uint16_t hal_uart_get_rx_fifo_level(uart_bus_t uart);
 
volatile uint32_t *hal_uart_get_data_register(uart_bus_t uart);
 
uint32_t hal_uart_get_error_status(uart_bus_t uart);
 
void hal_uart_set_baud_rate(uart_bus_t uart, uint32_t baud, uint32_t uart_clk);
 
uint32_t hal_uart_get_baud_rate(uart_bus_t uart, uint32_t uart_clk);
 
void hal_uart_set_data_bits(uart_bus_t uart, hal_uart_data_bit_t bits);
 
void hal_uart_set_stop_bits(uart_bus_t uart, hal_uart_stop_bit_t bits);
 
void hal_uart_set_parity(uart_bus_t uart, hal_uart_parity_t parity);
 
void hal_uart_disable_uart(uart_bus_t uart);
 
void hal_uart_enable_interrupt(uart_bus_t uart, hal_uart_interrupt_t interrupt_type, bool val);
 
void hal_uart_disable_interrupt(uart_bus_t uart, hal_uart_interrupt_t interrupt_type);
 
void hal_uart_clear_interrupt(uart_bus_t uart, hal_uart_interrupt_t interrupt_type);
 
uint32_t hal_uart_get_fifo_status(uart_bus_t uart);
 
void hal_uart_force_tx_isr(uart_bus_t uart);
 
void hal_uart_force_idle_isr(uart_bus_t uart);
 
bool hal_uart_switch_trx(uart_bus_t uart, bool switch_trx);
 
void hal_uart_isr(uart_bus_t uart);
 
void hal_uart_clear_pending(uart_bus_t uart);
 
void hal_uart_check_en(uart_bus_t uart, bool val);
 
void hal_uart_parity_en(uart_bus_t uart, hal_uart_parity_t val);
 
void hal_uart_sir_mode_en(uart_bus_t uart, bool val);
 
void hal_uart_tx_pause_en(uart_bus_t uart, bool val);
 
void hal_uart_set_baud_div(uart_bus_t uart, uint8_t val);
 
uint32_t hal_uart_get_baud_div(uart_bus_t uart);
 
#if defined(CONFIG_UART_IP_VERSION_V151_PRO)
void hal_uart_rx_en(uart_bus_t uart, bool val);
 
void hal_uart_set_lp_req_en(uart_bus_t uart, bool val);
#endif
 
uint32_t hal_uart_get_error_status(uart_bus_t uart);
 
bool hal_uart_get_error_status_parity(uart_bus_t uart);
 
bool hal_uart_get_error_status_fram(uart_bus_t uart);
 
bool hal_uart_get_error_status_break(uart_bus_t uart);
 
bool hal_uart_get_error_status_overrun(uart_bus_t uart);
 
void hal_uart_set_dmaen(uart_bus_t bus, uint32_t val);
 
static inline bool hal_uart_get_cpr_shadow(uart_bus_t uart)
{
    return ((uart_parameter_t)g_hal_uart_reg[uart]->uart_parameter).uart_parameter.shadow;
}
 
static inline uint16_t hal_uart_get_cpr_fifo_mode(uart_bus_t uart)
{
    return((uart_parameter_t)g_hal_uart_reg[uart]->uart_parameter).uart_parameter.fifo_depth;
}
 
static inline uint16_t hal_uart_get_cpr_afce_mode(uart_bus_t uart)
{
    return((uart_parameter_t)g_hal_uart_reg[uart]->uart_parameter).uart_parameter.afce_mode;
}
 
static inline uint16_t hal_uart_get_cpr_apb_data_width(uart_bus_t uart)
{
    return((uart_parameter_t)g_hal_uart_reg[uart]->uart_parameter).uart_parameter.apb_data_width;
}
 
static inline uint16_t hal_uart_get_cpr_dma_extra(uart_bus_t uart)
{
    return((uart_parameter_t)g_hal_uart_reg[uart]->uart_parameter).uart_parameter.dma_mode;
}
 
#endif