CHIP Platform CORE Driver 的协作图:

宏定义
#define	YES (1)

#define	NO (0)

#define	LOGGING_REGION_START get_hso_buff()

#define	LOGGING_REGION_LENGTH 0x1000

#define	GLB_CTL_M_RB_BASE 0x40002000

#define	GLB_CTL_B_RB_BASE 0x57000400

#define	GLB_CTL_D_RB_BASE 0x57000800

#define	DISPLAY_CTL_RB_BASE 0x56000000

#define	GPU_BASE_ADDR 0x56200000

#define	DSS_BASE_ADDR 0x56100000

#define	B_CTL_RB_BASE 0x59000000

#define	M_CTL_RB_BASE 0x52000000

#define	COM_CTL_RB_BASE 0x55000000

#define	PMU1_CTL_RB_BASE 0x40003000

#define	PMU2_CMU_CTL_RB_BASE 0x57008000

#define	ULP_AON_CTL_RB_ADDR 0x5702c000

#define	FUSE_CTL_RB_ADDR 0x57028000

#define	XO_CORE_TRIM_REG 0x57028308

#define	XO_CORE_CTRIM_REG 0x5702830c

#define	XIP_CACHE_CTL 0xA3006000

#define	NMI_CTL_REG_BASE_ADDR 0x52000700

#define	FLASH_START_ADDR 0x200000

#define	UART0_BASE 0x44010004 /* UART_L0 */

#define	UART1_BASE 0x44011004 /* UART_H0 */

#define	UART2_BASE 0x44012004 /* UART_H1 */

#define	DMA_BASE_ADDR 0x4A000000 /* M_DMA */

#define	SDMA_BASE_ADDR 0x520A0000 /* S_DMA */

#define	I2C_BUS_0_BASE_ADDR 0x44018000

#define	I2C_BUS_1_BASE_ADDR 0x44018100

#define	SPI_BUS_0_BASE_ADDR 0x44020000

#define	SPI_BUS_1_BASE_ADDR 0x44021000

#define	I2S_BUS_0_BASE_ADDR 0x4402503C

#define	DMA_HANDSHAKE_I2C_BUS_0_TX HAL_DMA_HANDSHAKING_I2C0_TX

#define	DMA_HANDSHAKE_I2C_BUS_0_RX HAL_DMA_HANDSHAKING_I2C0_RX

#define	DMA_HANDSHAKE_I2C_BUS_1_TX HAL_DMA_HANDSHAKING_I2C1_TX

#define	DMA_HANDSHAKE_I2C_BUS_1_RX HAL_DMA_HANDSHAKING_I2C1_RX

#define	DMA_HANDSHAKE_I2C_BUS_2_TX HAL_DMA_HANDSHAKING_I2C2_TX

#define	DMA_HANDSHAKE_I2C_BUS_2_RX HAL_DMA_HANDSHAKING_I2C2_RX

#define	DMA_HANDSHAKE_I2C_BUS_3_TX HAL_DMA_HANDSHAKING_I2C3_TX

#define	DMA_HANDSHAKE_I2C_BUS_3_RX HAL_DMA_HANDSHAKING_I2C3_RX

#define	DMA_HANDSHAKE_I2C_BUS_4_TX HAL_DMA_HANDSHAKING_I2C4_TX

#define	DMA_HANDSHAKE_I2C_BUS_4_RX HAL_DMA_HANDSHAKING_I2C4_RX

#define	HAL_SPI_DEVICE_MODE_SET_REG ((volatile unsigned short )(0x44000250))

#define	HAL_SPI3_MODE_SET_REG (M_CTL_RB_BASE + 0x950)

#define	PWM_0_BASE 0x44024000

#define	PWM_INTR_ENABLE_REG ((volatile unsigned short )0x52000900)

#define	PWM_INTR_CLEAR_REG ((volatile unsigned short )0x52000904)

#define	PWM_INTR_STATUS_REG ((volatile unsigned short )0x52000908)

#define	GPIO_CHANNEL_0_BASE_ADDR 0x44028000

#define	GPIO_CHANNEL_1_BASE_ADDR 0x44029000

#define	GPIO_CHANNEL_2_BASE_ADDR 0x4402A000

#define	ULP_GPIO_BASE_ADDR 0x57030000

#define	HAL_GPIO_D_CORE_SET_REG 0x570001B0

#define	HAL_GPIO_NON_D_CORE_SET_REG 0x57000180

#define	HAL_GPIO_CORE_SET_CHANNEL_OFFSET 0x08

#define	HAL_GPIO_CORE_SET_REG_OFFSET 2

#define	HAL_GPIO_CORE_SET_GPIOS 16

#define	HAL_GPIO_ULP_AON_GP_REG 0x5702C010

#define	HAL_GPIO_ULP_AON_PCLK_INT_EN_BIT 0

#define	HAL_GPIO_ULP_AON_PCLK_INT_CLK_SEL_BIT 1

#define	HAL_GPIO_ULP_PCLK_INTR_STATUS_BITS 0x3

#define	RTC_TIMER_BASE_ADDR 0x57024000

#define	SYSTICK_BASE_ADDR 0x40005000

#define	AFE_DIG_BASE_ADDRESS 0x57036000

#define	HAL_SOFT_RST_CTL_BASE (GLB_CTL_M_RB_BASE)

#define	HAL_GLB_CTL_M_ATOP1_L_REG_OFFSET 0x100

#define	HAL_CHIP_WDT_ATOP1_RST_BIT 4

#define	SEC_CTL_RB_BASE 0x52009000

#define	RSAV2_S_RB_BASE 0x52009900

#define	TRNG_RB_BASE 0x52009800

#define	TRACE_MEM_REGION_START MCPU_TRACE_MEM_REGION_START

#define	TRACE_MEM_REGION_LENGTH CPU_TRACE_MEM_REGION_LENGTH

#define	UART_BUS_MAX_NUMBER 3

#define	I2C_BUS_MAX_NUMBER 2

#define	SPI_BUS_MAX_NUMBER 2

#define	GPIO_MAX_NUMBER 3

#define	I2S_MAX_NUMBER 1

#define	S_DMA_CHANNEL_MAX_NUM 4

#define	B_DMA_CHANNEL_MAX_NUM 8

#define	DMA_CHANNEL_MAX_NUM (S_DMA_CHANNEL_MAX_NUM + B_DMA_CHANNEL_MAX_NUM)

#define	CHIP_BCPU_SWDDIO 0

#define	CHIP_BCPU_SWDCLK 0

#define	TEST_SUITE_UART_BUS CONFIG_TESTSUIT_UART

#define	TEST_SUITE_UART_TX_PIN S_AGPIO9

#define	TEST_SUITE_UART_RX_PIN S_AGPIO10

#define	CHIP_FIXED_TX_PIN S_AGPIO9

#define	CHIP_FIXED_RX_PIN S_AGPIO10

#define	SW_DEBUG_UART_BUS CONFIG_DEBUG_UART

#define	CHIP_FIXED_UART_BUS CONFIG_WVT_UART

#define	CODELOADER_UART_BUS UART_BUS_0

#define	CODELOADER_UART_TX_PIN S_AGPIO15

#define	CODELOADER_UART_RX_PIN S_AGPIO14

#define	LOG_UART_BUS CONFIG_LOG_UART

#define	LOG_UART_TX_PIN S_AGPIO12

#define	LOG_UART_RX_PIN S_AGPIO13

#define	AT_UART_BUS CONFIG_AT_UART

#define	QSPI_MAX_NUMBER 2

#define	FLASH_QSPI_ID QSPI_BUS_1

#define	QSPI_0_BASE_ADDR 0xA3000000

#define	QSPI_1_BASE_ADDR 0xA3002000

#define	MPU_REG_ADDR0_BASE 0x50000000

#define	MPU_REG_ADDR0_LEN 0x10000000

#define	MPU_REG_ADDR1_BASE 0xA3000000

#define	MPU_REG_ADDR1_LEN 0x01000000

#define	MPU_ROM_ADDR_BASE 0x0

#define	MPU_ROM_ADDR_LEN 0x8000

#define	MPU_ITCM_ADDR_BASE 0x80000

#define	MPU_ITCM_ADDR_LEN 0x80000

#define	MPU_L2RAM_ADDR0_BASE 0x100000

#define	MPU_L2RAM_ADDR0_LEN 0x100000

#define	MPU_L2RAM_ADDR1_BASE 0x200000

#define	MPU_L2RAM_ADDR1_LEN 0x100000

#define	MPU_XIP_PSRAM_RO_ADDR_BASE 0x08000000

#define	MPU_XIP_PSRAM_RO_ADDR_LEN 0x04000000

#define	MPU_XIP_PSRAM_RW_ADDR_BASE 0x0C000000

#define	MPU_XIP_PSRAM_RW_ADDR_LEN 0x04000000

#define	MPU_XIP_FLASE_RO_ADDR_BASE 0x10000000

#define	MPU_XIP_FLASE_RO_ADDR_LEN 0x10000000

#define	MPU_SHAREMEM_ADDR_BASE 0x87000000

#define	MPU_SHAREMEM_ADDR_LEN 0x10000

#define	MEM_X2P_MEMORY_START 0xA3000000

#define	MEM_X2P_MEMORY_END 0xA3008FFF

#define	L2RAM_MEMORY_START 0x00100000

#define	L2RAM_MEMORY_END 0x0035FFFF

#define	QSPI_XIP_MEMORY_START 0x08000000

#define	QSPI_XIP_MEMORY_END 0x1FFFFFFF

#define	CHIP_RESET_OFF 0x110

#define	PMU_RESERV1 0x570040C8

#define	HI_SFC_REG_BASE 0x48000000

#define	HI_SFC_FLASH1_BASE 0x48100000

#define	HI_SFC_MEM_SIZE 0x00800000

#define	S_MGPIO0 0

#define	S_MGPIO1 1

#define	S_MGPIO2 2

#define	S_MGPIO3 3

#define	S_MGPIO4 4

#define	S_MGPIO5 5

#define	S_MGPIO6 6

#define	S_MGPIO7 7

#define	S_MGPIO8 8

#define	S_MGPIO9 9

#define	S_MGPIO10 10

#define	S_MGPIO11 11

#define	S_MGPIO12 12

#define	S_MGPIO13 13

#define	S_MGPIO14 14

#define	S_MGPIO15 15

#define	S_MGPIO16 16

#define	S_MGPIO17 17

#define	S_MGPIO18 18

#define	S_MGPIO19 19

#define	S_MGPIO20 20

#define	S_MGPIO21 21

#define	S_MGPIO22 22

#define	S_MGPIO23 23

#define	S_MGPIO24 24

#define	S_MGPIO25 25

#define	S_MGPIO26 26

#define	S_MGPIO27 27

#define	S_MGPIO28 28

#define	S_MGPIO29 29

#define	S_MGPIO30 30

#define	S_MGPIO31 31

#define	S_AGPIO0 32

#define	S_AGPIO1 33

#define	S_AGPIO2 34

#define	S_AGPIO3 35

#define	S_AGPIO4 36

#define	S_AGPIO5 37

#define	S_AGPIO6 38

#define	S_AGPIO7 39

#define	S_AGPIO8 40

#define	S_AGPIO9 41

#define	S_AGPIO10 42

#define	S_AGPIO11 43

#define	S_AGPIO12 44

#define	S_AGPIO13 45

#define	S_AGPIO14 46

#define	S_AGPIO15 47

#define	S_AGPIO16 48

#define	S_AGPIO17 49

#define	S_AGPIO18 50

#define	S_AGPIO19 51

#define	S_HGPIO0 52

#define	S_HGPIO1 53

#define	S_HGPIO2 54

#define	S_HGPIO3 55

#define	S_HGPIO4 56

#define	S_HGPIO5 57

#define	L_HGPIO0 64

#define	L_HGPIO11 75

#define	L_AGPIO0 76

#define	L_AGPIO1 77

#define	L_AGPIO2 78

#define	L_AGPIO3 79

#define	L_AGPIO8 84

#define	L_MGPIO0 85

#define	L_MGPIO1 86

#define	L_MGPIO2 87

#define	L_MGPIO3 88

#define	L_MGPIO4 89

#define	L_MGPIO5 90

#define	L_MGPIO6 91

#define	L_MGPIO7 92

#define	L_MGPIO8 93

#define	L_MGPIO9 94

#define	L_MGPIO10 95

#define	L_MGPIO11 96

#define	L_MGPIO12 97

#define	L_MGPIO13 98

#define	L_MGPIO14 99

#define	L_MGPIO15 100

#define	L_MGPIO16 101

#define	L_MGPIO17 102

#define	L_MGPIO18 103

#define	L_MGPIO19 104

#define	L_MGPIO31 104

#define	L_MGPIO47 104

#define	L_MGPIO57 104

#define	SYS_RSTN 105

#define	RTC_CLK 106

#define	ULP_GPIO0 107

#define	ULP_GPIO1 108

#define	ULP_GPIO2 109

#define	ULP_GPIO3 110

#define	PWR_HOLD 111

#define	HRESET 112

#define	SLEEP_N 113

#define	PMUIC_IRQ 114

#define	PIN_NONE 115

#define	ULP_PIN SYS_RSTN

#define	TCXO_COUNT_ENABLE YES

#define	LOW_POWER_WR15_CS_ENHANCE YES

#define	WATCHDOG_ROM_ENABLE YES

#define	GPIO_WITH_ULP YES

#define	GPIO_FUNC HAL_PIO_FUNC_GPIO

#define	I2C_AUTO_SEND_STOP_CMD NO

#define	I2C_WITH_BUS_RECOVERY YES

#define	SPI_WITH_OPI NO

#define	SPI_DMA_TRANSFER_NUM_BY_BYTE NO

#define	DMA_TRANSFER_DEBUG YES

#define	DMA_USE_HIDMA NO

#define	DMA_WITH_MDMA YES

#define	DMA_WITH_SMDMA YES

#define	DMA_TRANS_BY_LLI NO

#define	XIP_WITH_OPI YES

#define	XIP_INT_BY_NMI YES

#define	EFLASH_SLAVE_NOTIFY_MASTER_BOOTUP YES

#define	ENABLE_CPU_TRACE 2

#define	ADC_WITH_AUTO_SCAN YES

#define	OTP_HAS_READ_PERMISSION YES

#define	OTP_HAS_WRITE_PERMISSION YES

#define	OTP_HAS_CLKLDO_VSET NO

#define	SEC_IAMGE_AES_DECRYPT_EN NO

#define	SEC_BOOT_SIGN_CHECK_EN YES

#define	SEC_SUB_RST_BY_SECURITY_CORE NO

#define	TRNG_WITH_SEC_COMMON YES

#define	IS_MAIN_CORE YES

#define	EXTERNAL_CLOCK_CALIBRATION YES

#define	AON_SPECIAL_PIO YES

#define	SUPPORT_HI_EMMC_PHY NO

#define	OPI_PIN_FIX_DM1_DRIVER NO

#define	OPI_USE_MCU_HS_CLK NO

#define	QSPI0_FUNC HAL_PIO_FUNC_QSPI0

#define	QSPI0_D0 S_MGPIO0

#define	QSPI0_D1 S_MGPIO1

#define	QSPI0_D2 S_MGPIO2

#define	QSPI0_D3 S_MGPIO3

#define	QSPI0_CLK S_MGPIO4

#define	QSPI0_CS S_MGPIO5

#define	QSPI1_FUNC HAL_PIO_FUNC_QSPI1

#define	QSPI1_D0 S_MGPIO6

#define	QSPI1_D1 S_MGPIO7

#define	QSPI1_D2 S_MGPIO8

#define	QSPI1_D3 S_MGPIO9

#define	QSPI1_CLK S_MGPIO10

#define	QSPI1_CS S_MGPIO11

#define	XIP_EXIST YES

#define	USE_XIP_INDEX 1

#define	BCPU_INT0_ID 26

#define	UART_BAUD_RATE_DIV_8 NO

#define	FIXED_IN_ROM NO

#define	PMU_LPM_WAKEUP_SRC_NUM 16

#define	ENABLE_GPIO_INTERRUPT YES

#define	CLK_AUTO_CG_ENABLE NO

#define	BOOT_ROM_DFR_PRINT NO

#define	EFLASH_WRITE_CLK_DIV_AUTO_ADJ NO

#define	DMA_WITH_MUX_CHANNEL YES

#define	CRITICAL_INT_RESTORE YES

#define	SEC_TRNG_ENABLE NO

#define	DCACHE_IS_ENABLE NO

#define	CODELOADER_SINGLE_PARTITION_EXP YES

#define	AUXLDO_ENABLE_FLASH NO

#define	TCXO_CLK_DYN_ADJUST NO

#define	SUPPORT_PARTITION_FEATURE NO

#define	SUPPORT_SINGLE_DSP_DUAL_IMAGE NO

枚举
enum	qspi_bus_t { QSPI_BUS_0 = 0 , QSPI_BUS_1 , QSPI_BUS_NONE = 2 }

enum	uart_bus_t { UART_BUS_0 = 0 , UART_BUS_1 = 1 , UART_BUS_2 = 2 , UART_BUS_NONE = 3 }
	UART bus. 更多...

enum	i2c_bus_t { I2C_BUS_0 , I2C_BUS_1 , I2C_BUS_NONE = 2 }
	I2C bus. 更多...

enum	spi_bus_t { SPI_BUS_0 = 0 , SPI_BUS_1 , SPI_BUS_2 , SPI_BUS_3 , SPI_BUS_4 , SPI_BUS_5 , SPI_BUS_6 , SPI_BUS_NONE = 2 }
	Definition of SPI bus index. 更多...

enum	sio_bus_t { SIO_BUS_0 , SIO_NONE = 1 }
	SIO(I2S/PCM) Bus. 更多...

enum	slave_cpu_t { SLAVE_CPU_BT , SLAVE_CPU_MAX_NUM }

函数
unsigned int	get_hso_buff (void)

enum	pin_t { GPIO_00 = 0 , GPIO_01 = 1 , GPIO_02 = 2 , GPIO_03 = 3 , GPIO_04 = 4 , GPIO_05 = 5 , GPIO_06 = 6 , GPIO_07 = 7 , GPIO_08 = 8 , GPIO_09 = 9 , GPIO_10 = 10 , GPIO_11 = 11 , GPIO_12 = 12 , GPIO_13 = 13 , GPIO_14 = 14 , GPIO_15 = 15 , GPIO_16 = 16 , GPIO_17 = 17 , GPIO_18 = 18 , SFC_CLK = 19 , SFC_CSN = 20 , SFC_IO0 = 21 , SFC_IO1 = 22 , SFC_IO2 = 23 , SFC_IO3 = 24 , PIN_NONE = 25 }
	Definition of pin. 更多...

#define	TIMER_BASE_ADDR 0x44002000

#define	TIMER_0_BASE_ADDR (TIMER_BASE_ADDR + 0x100)

#define	TIMER_1_BASE_ADDR (TIMER_BASE_ADDR + 0x200)

#define	TIMER_2_BASE_ADDR (TIMER_BASE_ADDR + 0x300)

#define	TIMER_SYSCTL_BASE_ADDR (TIMER_BASE_ADDR + 0xA0)

#define	TICK_TIMER_BASE_ADDR TIMER_0_BASE_ADDR

#define	TCXO_COUNT_BASE_ADDR 0x440004C0

#define	PIN_MAX_NUMBER PIN_NONE

#define	CHIP_WDT_BASE_ADDRESS 0x40006000

详细描述

宏定义说明

◆ ADC_WITH_AUTO_SCAN

#define ADC_WITH_AUTO_SCAN YES

◆ AFE_DIG_BASE_ADDRESS

#define AFE_DIG_BASE_ADDRESS 0x57036000

◆ AON_SPECIAL_PIO

#define AON_SPECIAL_PIO YES

◆ AT_UART_BUS

#define AT_UART_BUS CONFIG_AT_UART

◆ AUXLDO_ENABLE_FLASH

#define AUXLDO_ENABLE_FLASH NO

◆ B_CTL_RB_BASE

#define B_CTL_RB_BASE 0x59000000

◆ B_DMA_CHANNEL_MAX_NUM

#define B_DMA_CHANNEL_MAX_NUM 8

◆ BCPU_INT0_ID

#define BCPU_INT0_ID 26

◆ BOOT_ROM_DFR_PRINT

#define BOOT_ROM_DFR_PRINT NO

◆ CHIP_BCPU_SWDCLK

#define CHIP_BCPU_SWDCLK 0

◆ CHIP_BCPU_SWDDIO

#define CHIP_BCPU_SWDDIO 0

◆ CHIP_FIXED_RX_PIN

#define CHIP_FIXED_RX_PIN S_AGPIO10

◆ CHIP_FIXED_TX_PIN

#define CHIP_FIXED_TX_PIN S_AGPIO9

◆ CHIP_FIXED_UART_BUS

#define CHIP_FIXED_UART_BUS CONFIG_WVT_UART

◆ CHIP_RESET_OFF

#define CHIP_RESET_OFF 0x110

◆ CHIP_WDT_BASE_ADDRESS

#define CHIP_WDT_BASE_ADDRESS 0x40006000

◆ CLK_AUTO_CG_ENABLE

#define CLK_AUTO_CG_ENABLE NO

◆ CODELOADER_SINGLE_PARTITION_EXP

#define CODELOADER_SINGLE_PARTITION_EXP YES

◆ CODELOADER_UART_BUS

#define CODELOADER_UART_BUS UART_BUS_0

◆ CODELOADER_UART_RX_PIN

#define CODELOADER_UART_RX_PIN S_AGPIO14

◆ CODELOADER_UART_TX_PIN

#define CODELOADER_UART_TX_PIN S_AGPIO15

◆ COM_CTL_RB_BASE

#define COM_CTL_RB_BASE 0x55000000

◆ CRITICAL_INT_RESTORE

#define CRITICAL_INT_RESTORE YES

◆ DCACHE_IS_ENABLE

#define DCACHE_IS_ENABLE NO

◆ DISPLAY_CTL_RB_BASE

#define DISPLAY_CTL_RB_BASE 0x56000000

◆ DMA_BASE_ADDR

#define DMA_BASE_ADDR 0x4A000000 /* M_DMA */

◆ DMA_CHANNEL_MAX_NUM

#define DMA_CHANNEL_MAX_NUM (S_DMA_CHANNEL_MAX_NUM + B_DMA_CHANNEL_MAX_NUM)

◆ DMA_HANDSHAKE_I2C_BUS_0_RX

#define DMA_HANDSHAKE_I2C_BUS_0_RX HAL_DMA_HANDSHAKING_I2C0_RX

◆ DMA_HANDSHAKE_I2C_BUS_0_TX

#define DMA_HANDSHAKE_I2C_BUS_0_TX HAL_DMA_HANDSHAKING_I2C0_TX

◆ DMA_HANDSHAKE_I2C_BUS_1_RX

#define DMA_HANDSHAKE_I2C_BUS_1_RX HAL_DMA_HANDSHAKING_I2C1_RX

◆ DMA_HANDSHAKE_I2C_BUS_1_TX

#define DMA_HANDSHAKE_I2C_BUS_1_TX HAL_DMA_HANDSHAKING_I2C1_TX

◆ DMA_HANDSHAKE_I2C_BUS_2_RX

#define DMA_HANDSHAKE_I2C_BUS_2_RX HAL_DMA_HANDSHAKING_I2C2_RX

◆ DMA_HANDSHAKE_I2C_BUS_2_TX

#define DMA_HANDSHAKE_I2C_BUS_2_TX HAL_DMA_HANDSHAKING_I2C2_TX

◆ DMA_HANDSHAKE_I2C_BUS_3_RX

#define DMA_HANDSHAKE_I2C_BUS_3_RX HAL_DMA_HANDSHAKING_I2C3_RX

◆ DMA_HANDSHAKE_I2C_BUS_3_TX

#define DMA_HANDSHAKE_I2C_BUS_3_TX HAL_DMA_HANDSHAKING_I2C3_TX

◆ DMA_HANDSHAKE_I2C_BUS_4_RX

#define DMA_HANDSHAKE_I2C_BUS_4_RX HAL_DMA_HANDSHAKING_I2C4_RX

◆ DMA_HANDSHAKE_I2C_BUS_4_TX

#define DMA_HANDSHAKE_I2C_BUS_4_TX HAL_DMA_HANDSHAKING_I2C4_TX

◆ DMA_TRANS_BY_LLI

#define DMA_TRANS_BY_LLI NO

◆ DMA_TRANSFER_DEBUG

#define DMA_TRANSFER_DEBUG YES

◆ DMA_USE_HIDMA

#define DMA_USE_HIDMA NO

◆ DMA_WITH_MDMA

#define DMA_WITH_MDMA YES

◆ DMA_WITH_MUX_CHANNEL

#define DMA_WITH_MUX_CHANNEL YES

◆ DMA_WITH_SMDMA

#define DMA_WITH_SMDMA YES

◆ DSS_BASE_ADDR

#define DSS_BASE_ADDR 0x56100000

◆ EFLASH_SLAVE_NOTIFY_MASTER_BOOTUP

#define EFLASH_SLAVE_NOTIFY_MASTER_BOOTUP YES

◆ EFLASH_WRITE_CLK_DIV_AUTO_ADJ

#define EFLASH_WRITE_CLK_DIV_AUTO_ADJ NO

◆ ENABLE_CPU_TRACE

#define ENABLE_CPU_TRACE 2

◆ ENABLE_GPIO_INTERRUPT

#define ENABLE_GPIO_INTERRUPT YES

◆ EXTERNAL_CLOCK_CALIBRATION

#define EXTERNAL_CLOCK_CALIBRATION YES

◆ FIXED_IN_ROM

#define FIXED_IN_ROM NO

◆ FLASH_QSPI_ID

#define FLASH_QSPI_ID QSPI_BUS_1

◆ FLASH_START_ADDR

#define FLASH_START_ADDR 0x200000

◆ FUSE_CTL_RB_ADDR

#define FUSE_CTL_RB_ADDR 0x57028000

◆ GLB_CTL_B_RB_BASE

#define GLB_CTL_B_RB_BASE 0x57000400

◆ GLB_CTL_D_RB_BASE

#define GLB_CTL_D_RB_BASE 0x57000800

◆ GLB_CTL_M_RB_BASE

#define GLB_CTL_M_RB_BASE 0x40002000

◆ GPIO_CHANNEL_0_BASE_ADDR

#define GPIO_CHANNEL_0_BASE_ADDR 0x44028000

◆ GPIO_CHANNEL_1_BASE_ADDR

#define GPIO_CHANNEL_1_BASE_ADDR 0x44029000

◆ GPIO_CHANNEL_2_BASE_ADDR

#define GPIO_CHANNEL_2_BASE_ADDR 0x4402A000

◆ GPIO_FUNC

#define GPIO_FUNC HAL_PIO_FUNC_GPIO

◆ GPIO_MAX_NUMBER

#define GPIO_MAX_NUMBER 3

◆ GPIO_WITH_ULP

#define GPIO_WITH_ULP YES

◆ GPU_BASE_ADDR

#define GPU_BASE_ADDR 0x56200000

◆ HAL_CHIP_WDT_ATOP1_RST_BIT

#define HAL_CHIP_WDT_ATOP1_RST_BIT 4

◆ HAL_GLB_CTL_M_ATOP1_L_REG_OFFSET

#define HAL_GLB_CTL_M_ATOP1_L_REG_OFFSET 0x100

◆ HAL_GPIO_CORE_SET_CHANNEL_OFFSET

#define HAL_GPIO_CORE_SET_CHANNEL_OFFSET 0x08

◆ HAL_GPIO_CORE_SET_GPIOS

#define HAL_GPIO_CORE_SET_GPIOS 16

◆ HAL_GPIO_CORE_SET_REG_OFFSET

#define HAL_GPIO_CORE_SET_REG_OFFSET 2

◆ HAL_GPIO_D_CORE_SET_REG

#define HAL_GPIO_D_CORE_SET_REG 0x570001B0

◆ HAL_GPIO_NON_D_CORE_SET_REG

#define HAL_GPIO_NON_D_CORE_SET_REG 0x57000180

◆ HAL_GPIO_ULP_AON_GP_REG

#define HAL_GPIO_ULP_AON_GP_REG 0x5702C010

◆ HAL_GPIO_ULP_AON_PCLK_INT_CLK_SEL_BIT

#define HAL_GPIO_ULP_AON_PCLK_INT_CLK_SEL_BIT 1

◆ HAL_GPIO_ULP_AON_PCLK_INT_EN_BIT

#define HAL_GPIO_ULP_AON_PCLK_INT_EN_BIT 0

◆ HAL_GPIO_ULP_PCLK_INTR_STATUS_BITS

#define HAL_GPIO_ULP_PCLK_INTR_STATUS_BITS 0x3

◆ HAL_SOFT_RST_CTL_BASE

#define HAL_SOFT_RST_CTL_BASE (GLB_CTL_M_RB_BASE)

◆ HAL_SPI3_MODE_SET_REG

#define HAL_SPI3_MODE_SET_REG (M_CTL_RB_BASE + 0x950)

◆ HAL_SPI_DEVICE_MODE_SET_REG

#define HAL_SPI_DEVICE_MODE_SET_REG (*(volatile unsigned short *)(0x44000250))

◆ HI_SFC_FLASH1_BASE

#define HI_SFC_FLASH1_BASE 0x48100000

◆ HI_SFC_MEM_SIZE

#define HI_SFC_MEM_SIZE 0x00800000

◆ HI_SFC_REG_BASE

#define HI_SFC_REG_BASE 0x48000000

◆ HRESET

#define HRESET 112

◆ I2C_AUTO_SEND_STOP_CMD

#define I2C_AUTO_SEND_STOP_CMD NO

◆ I2C_BUS_0_BASE_ADDR

#define I2C_BUS_0_BASE_ADDR 0x44018000

◆ I2C_BUS_1_BASE_ADDR

#define I2C_BUS_1_BASE_ADDR 0x44018100

◆ I2C_BUS_MAX_NUMBER

#define I2C_BUS_MAX_NUMBER 2

◆ I2C_WITH_BUS_RECOVERY

#define I2C_WITH_BUS_RECOVERY YES

◆ I2S_BUS_0_BASE_ADDR

#define I2S_BUS_0_BASE_ADDR 0x4402503C

◆ I2S_MAX_NUMBER

#define I2S_MAX_NUMBER 1

◆ IS_MAIN_CORE

#define IS_MAIN_CORE YES

◆ L2RAM_MEMORY_END

#define L2RAM_MEMORY_END 0x0035FFFF

◆ L2RAM_MEMORY_START

#define L2RAM_MEMORY_START 0x00100000

◆ L_AGPIO0

#define L_AGPIO0 76

◆ L_AGPIO1

#define L_AGPIO1 77

◆ L_AGPIO2

#define L_AGPIO2 78

◆ L_AGPIO3

#define L_AGPIO3 79

◆ L_AGPIO8

#define L_AGPIO8 84

◆ L_HGPIO0

#define L_HGPIO0 64

◆ L_HGPIO11

#define L_HGPIO11 75

◆ L_MGPIO0

#define L_MGPIO0 85

◆ L_MGPIO1

#define L_MGPIO1 86

◆ L_MGPIO10

#define L_MGPIO10 95

◆ L_MGPIO11

#define L_MGPIO11 96

◆ L_MGPIO12

#define L_MGPIO12 97

◆ L_MGPIO13

#define L_MGPIO13 98

◆ L_MGPIO14

#define L_MGPIO14 99

◆ L_MGPIO15

#define L_MGPIO15 100

◆ L_MGPIO16

#define L_MGPIO16 101

◆ L_MGPIO17

#define L_MGPIO17 102

◆ L_MGPIO18

#define L_MGPIO18 103

◆ L_MGPIO19

#define L_MGPIO19 104

◆ L_MGPIO2

#define L_MGPIO2 87

◆ L_MGPIO3

#define L_MGPIO3 88

◆ L_MGPIO31

#define L_MGPIO31 104

◆ L_MGPIO4

#define L_MGPIO4 89

◆ L_MGPIO47

#define L_MGPIO47 104

◆ L_MGPIO5

#define L_MGPIO5 90

◆ L_MGPIO57

#define L_MGPIO57 104

◆ L_MGPIO6

#define L_MGPIO6 91

◆ L_MGPIO7

#define L_MGPIO7 92

◆ L_MGPIO8

#define L_MGPIO8 93

◆ L_MGPIO9

#define L_MGPIO9 94

◆ LOG_UART_BUS

#define LOG_UART_BUS CONFIG_LOG_UART

◆ LOG_UART_RX_PIN

#define LOG_UART_RX_PIN S_AGPIO13

◆ LOG_UART_TX_PIN

#define LOG_UART_TX_PIN S_AGPIO12

◆ LOGGING_REGION_LENGTH

#define LOGGING_REGION_LENGTH 0x1000

◆ LOGGING_REGION_START

#define LOGGING_REGION_START get_hso_buff()

◆ LOW_POWER_WR15_CS_ENHANCE

#define LOW_POWER_WR15_CS_ENHANCE YES

◆ M_CTL_RB_BASE

#define M_CTL_RB_BASE 0x52000000

◆ MEM_X2P_MEMORY_END

#define MEM_X2P_MEMORY_END 0xA3008FFF

◆ MEM_X2P_MEMORY_START

#define MEM_X2P_MEMORY_START 0xA3000000

◆ MPU_ITCM_ADDR_BASE

#define MPU_ITCM_ADDR_BASE 0x80000

◆ MPU_ITCM_ADDR_LEN

#define MPU_ITCM_ADDR_LEN 0x80000

◆ MPU_L2RAM_ADDR0_BASE

#define MPU_L2RAM_ADDR0_BASE 0x100000

◆ MPU_L2RAM_ADDR0_LEN

#define MPU_L2RAM_ADDR0_LEN 0x100000

◆ MPU_L2RAM_ADDR1_BASE

#define MPU_L2RAM_ADDR1_BASE 0x200000

◆ MPU_L2RAM_ADDR1_LEN

#define MPU_L2RAM_ADDR1_LEN 0x100000

◆ MPU_REG_ADDR0_BASE

#define MPU_REG_ADDR0_BASE 0x50000000

◆ MPU_REG_ADDR0_LEN

#define MPU_REG_ADDR0_LEN 0x10000000

◆ MPU_REG_ADDR1_BASE

#define MPU_REG_ADDR1_BASE 0xA3000000

◆ MPU_REG_ADDR1_LEN

#define MPU_REG_ADDR1_LEN 0x01000000

◆ MPU_ROM_ADDR_BASE

#define MPU_ROM_ADDR_BASE 0x0

◆ MPU_ROM_ADDR_LEN

#define MPU_ROM_ADDR_LEN 0x8000

◆ MPU_SHAREMEM_ADDR_BASE

#define MPU_SHAREMEM_ADDR_BASE 0x87000000

◆ MPU_SHAREMEM_ADDR_LEN

#define MPU_SHAREMEM_ADDR_LEN 0x10000

◆ MPU_XIP_FLASE_RO_ADDR_BASE

#define MPU_XIP_FLASE_RO_ADDR_BASE 0x10000000

◆ MPU_XIP_FLASE_RO_ADDR_LEN

#define MPU_XIP_FLASE_RO_ADDR_LEN 0x10000000

◆ MPU_XIP_PSRAM_RO_ADDR_BASE

#define MPU_XIP_PSRAM_RO_ADDR_BASE 0x08000000

◆ MPU_XIP_PSRAM_RO_ADDR_LEN

#define MPU_XIP_PSRAM_RO_ADDR_LEN 0x04000000

◆ MPU_XIP_PSRAM_RW_ADDR_BASE

#define MPU_XIP_PSRAM_RW_ADDR_BASE 0x0C000000

◆ MPU_XIP_PSRAM_RW_ADDR_LEN

#define MPU_XIP_PSRAM_RW_ADDR_LEN 0x04000000

◆ NMI_CTL_REG_BASE_ADDR

#define NMI_CTL_REG_BASE_ADDR 0x52000700

◆ NO

#define NO (0)

◆ OPI_PIN_FIX_DM1_DRIVER

#define OPI_PIN_FIX_DM1_DRIVER NO

◆ OPI_USE_MCU_HS_CLK

#define OPI_USE_MCU_HS_CLK NO

◆ OTP_HAS_CLKLDO_VSET

#define OTP_HAS_CLKLDO_VSET NO

◆ OTP_HAS_READ_PERMISSION

#define OTP_HAS_READ_PERMISSION YES

◆ OTP_HAS_WRITE_PERMISSION

#define OTP_HAS_WRITE_PERMISSION YES

◆ PIN_MAX_NUMBER

#define PIN_MAX_NUMBER PIN_NONE

◆ PIN_NONE

#define PIN_NONE 115

◆ PMU1_CTL_RB_BASE

#define PMU1_CTL_RB_BASE 0x40003000

◆ PMU2_CMU_CTL_RB_BASE

#define PMU2_CMU_CTL_RB_BASE 0x57008000

◆ PMU_LPM_WAKEUP_SRC_NUM

#define PMU_LPM_WAKEUP_SRC_NUM 16

◆ PMU_RESERV1

#define PMU_RESERV1 0x570040C8

◆ PMUIC_IRQ

#define PMUIC_IRQ 114

◆ PWM_0_BASE

#define PWM_0_BASE 0x44024000

◆ PWM_INTR_CLEAR_REG

#define PWM_INTR_CLEAR_REG (*(volatile unsigned short *)0x52000904)

◆ PWM_INTR_ENABLE_REG

#define PWM_INTR_ENABLE_REG (*(volatile unsigned short *)0x52000900)

◆ PWM_INTR_STATUS_REG

#define PWM_INTR_STATUS_REG (*(volatile unsigned short *)0x52000908)

◆ PWR_HOLD

#define PWR_HOLD 111

◆ QSPI0_CLK

#define QSPI0_CLK S_MGPIO4

◆ QSPI0_CS

#define QSPI0_CS S_MGPIO5

◆ QSPI0_D0

#define QSPI0_D0 S_MGPIO0

◆ QSPI0_D1

#define QSPI0_D1 S_MGPIO1

◆ QSPI0_D2

#define QSPI0_D2 S_MGPIO2

◆ QSPI0_D3

#define QSPI0_D3 S_MGPIO3

◆ QSPI0_FUNC

#define QSPI0_FUNC HAL_PIO_FUNC_QSPI0

◆ QSPI1_CLK

#define QSPI1_CLK S_MGPIO10

◆ QSPI1_CS

#define QSPI1_CS S_MGPIO11

◆ QSPI1_D0

#define QSPI1_D0 S_MGPIO6

◆ QSPI1_D1

#define QSPI1_D1 S_MGPIO7

◆ QSPI1_D2

#define QSPI1_D2 S_MGPIO8

◆ QSPI1_D3

#define QSPI1_D3 S_MGPIO9

◆ QSPI1_FUNC

#define QSPI1_FUNC HAL_PIO_FUNC_QSPI1

◆ QSPI_0_BASE_ADDR

#define QSPI_0_BASE_ADDR 0xA3000000

◆ QSPI_1_BASE_ADDR

#define QSPI_1_BASE_ADDR 0xA3002000

◆ QSPI_MAX_NUMBER

#define QSPI_MAX_NUMBER 2

◆ QSPI_XIP_MEMORY_END

#define QSPI_XIP_MEMORY_END 0x1FFFFFFF

◆ QSPI_XIP_MEMORY_START

#define QSPI_XIP_MEMORY_START 0x08000000

◆ RSAV2_S_RB_BASE

#define RSAV2_S_RB_BASE 0x52009900

◆ RTC_CLK

#define RTC_CLK 106

◆ RTC_TIMER_BASE_ADDR

#define RTC_TIMER_BASE_ADDR 0x57024000

◆ S_AGPIO0

#define S_AGPIO0 32

◆ S_AGPIO1

#define S_AGPIO1 33

◆ S_AGPIO10

#define S_AGPIO10 42

◆ S_AGPIO11

#define S_AGPIO11 43

◆ S_AGPIO12

#define S_AGPIO12 44

◆ S_AGPIO13

#define S_AGPIO13 45

◆ S_AGPIO14

#define S_AGPIO14 46

◆ S_AGPIO15

#define S_AGPIO15 47

◆ S_AGPIO16

#define S_AGPIO16 48

◆ S_AGPIO17

#define S_AGPIO17 49

◆ S_AGPIO18

#define S_AGPIO18 50

◆ S_AGPIO19

#define S_AGPIO19 51

◆ S_AGPIO2

#define S_AGPIO2 34

◆ S_AGPIO3

#define S_AGPIO3 35

◆ S_AGPIO4

#define S_AGPIO4 36

◆ S_AGPIO5

#define S_AGPIO5 37

◆ S_AGPIO6

#define S_AGPIO6 38

◆ S_AGPIO7

#define S_AGPIO7 39

◆ S_AGPIO8

#define S_AGPIO8 40

◆ S_AGPIO9

#define S_AGPIO9 41

◆ S_DMA_CHANNEL_MAX_NUM

#define S_DMA_CHANNEL_MAX_NUM 4

◆ S_HGPIO0

#define S_HGPIO0 52

◆ S_HGPIO1

#define S_HGPIO1 53

◆ S_HGPIO2

#define S_HGPIO2 54

◆ S_HGPIO3

#define S_HGPIO3 55

◆ S_HGPIO4

#define S_HGPIO4 56

◆ S_HGPIO5

#define S_HGPIO5 57

◆ S_MGPIO0

#define S_MGPIO0 0

◆ S_MGPIO1

#define S_MGPIO1 1

◆ S_MGPIO10

#define S_MGPIO10 10

◆ S_MGPIO11

#define S_MGPIO11 11

◆ S_MGPIO12

#define S_MGPIO12 12

◆ S_MGPIO13

#define S_MGPIO13 13

◆ S_MGPIO14

#define S_MGPIO14 14

◆ S_MGPIO15

#define S_MGPIO15 15

◆ S_MGPIO16

#define S_MGPIO16 16

◆ S_MGPIO17

#define S_MGPIO17 17

◆ S_MGPIO18

#define S_MGPIO18 18

◆ S_MGPIO19

#define S_MGPIO19 19

◆ S_MGPIO2

#define S_MGPIO2 2

◆ S_MGPIO20

#define S_MGPIO20 20

◆ S_MGPIO21

#define S_MGPIO21 21

◆ S_MGPIO22

#define S_MGPIO22 22

◆ S_MGPIO23

#define S_MGPIO23 23

◆ S_MGPIO24

#define S_MGPIO24 24

◆ S_MGPIO25

#define S_MGPIO25 25

◆ S_MGPIO26

#define S_MGPIO26 26

◆ S_MGPIO27

#define S_MGPIO27 27

◆ S_MGPIO28

#define S_MGPIO28 28

◆ S_MGPIO29

#define S_MGPIO29 29

◆ S_MGPIO3

#define S_MGPIO3 3

◆ S_MGPIO30

#define S_MGPIO30 30

◆ S_MGPIO31

#define S_MGPIO31 31

◆ S_MGPIO4

#define S_MGPIO4 4

◆ S_MGPIO5

#define S_MGPIO5 5

◆ S_MGPIO6

#define S_MGPIO6 6

◆ S_MGPIO7

#define S_MGPIO7 7

◆ S_MGPIO8

#define S_MGPIO8 8

◆ S_MGPIO9

#define S_MGPIO9 9

◆ SDMA_BASE_ADDR

#define SDMA_BASE_ADDR 0x520A0000 /* S_DMA */

◆ SEC_BOOT_SIGN_CHECK_EN

#define SEC_BOOT_SIGN_CHECK_EN YES

◆ SEC_CTL_RB_BASE

#define SEC_CTL_RB_BASE 0x52009000

◆ SEC_IAMGE_AES_DECRYPT_EN

#define SEC_IAMGE_AES_DECRYPT_EN NO

◆ SEC_SUB_RST_BY_SECURITY_CORE

#define SEC_SUB_RST_BY_SECURITY_CORE NO

◆ SEC_TRNG_ENABLE

#define SEC_TRNG_ENABLE NO

◆ SLEEP_N

#define SLEEP_N 113

◆ SPI_BUS_0_BASE_ADDR

#define SPI_BUS_0_BASE_ADDR 0x44020000

◆ SPI_BUS_1_BASE_ADDR

#define SPI_BUS_1_BASE_ADDR 0x44021000

◆ SPI_BUS_MAX_NUMBER

#define SPI_BUS_MAX_NUMBER 2

◆ SPI_DMA_TRANSFER_NUM_BY_BYTE

#define SPI_DMA_TRANSFER_NUM_BY_BYTE NO

◆ SPI_WITH_OPI

#define SPI_WITH_OPI NO

◆ SUPPORT_HI_EMMC_PHY

#define SUPPORT_HI_EMMC_PHY NO

◆ SUPPORT_PARTITION_FEATURE

#define SUPPORT_PARTITION_FEATURE NO

◆ SUPPORT_SINGLE_DSP_DUAL_IMAGE

#define SUPPORT_SINGLE_DSP_DUAL_IMAGE NO

◆ SW_DEBUG_UART_BUS

#define SW_DEBUG_UART_BUS CONFIG_DEBUG_UART

◆ SYS_RSTN

#define SYS_RSTN 105

◆ SYSTICK_BASE_ADDR

#define SYSTICK_BASE_ADDR 0x40005000

◆ TCXO_CLK_DYN_ADJUST

#define TCXO_CLK_DYN_ADJUST NO

◆ TCXO_COUNT_BASE_ADDR

#define TCXO_COUNT_BASE_ADDR 0x440004C0

◆ TCXO_COUNT_ENABLE

#define TCXO_COUNT_ENABLE YES

◆ TEST_SUITE_UART_BUS

#define TEST_SUITE_UART_BUS CONFIG_TESTSUIT_UART

◆ TEST_SUITE_UART_RX_PIN

#define TEST_SUITE_UART_RX_PIN S_AGPIO10

◆ TEST_SUITE_UART_TX_PIN

#define TEST_SUITE_UART_TX_PIN S_AGPIO9

◆ TICK_TIMER_BASE_ADDR

#define TICK_TIMER_BASE_ADDR TIMER_0_BASE_ADDR

◆ TIMER_0_BASE_ADDR

#define TIMER_0_BASE_ADDR (TIMER_BASE_ADDR + 0x100)

◆ TIMER_1_BASE_ADDR

#define TIMER_1_BASE_ADDR (TIMER_BASE_ADDR + 0x200)

◆ TIMER_2_BASE_ADDR

#define TIMER_2_BASE_ADDR (TIMER_BASE_ADDR + 0x300)

◆ TIMER_BASE_ADDR

#define TIMER_BASE_ADDR 0x44002000

◆ TIMER_SYSCTL_BASE_ADDR

#define TIMER_SYSCTL_BASE_ADDR (TIMER_BASE_ADDR + 0xA0)

◆ TRACE_MEM_REGION_LENGTH

#define TRACE_MEM_REGION_LENGTH CPU_TRACE_MEM_REGION_LENGTH

◆ TRACE_MEM_REGION_START

#define TRACE_MEM_REGION_START MCPU_TRACE_MEM_REGION_START

◆ TRNG_RB_BASE

#define TRNG_RB_BASE 0x52009800

◆ TRNG_WITH_SEC_COMMON

#define TRNG_WITH_SEC_COMMON YES

◆ UART0_BASE

#define UART0_BASE 0x44010004 /* UART_L0 */

◆ UART1_BASE

#define UART1_BASE 0x44011004 /* UART_H0 */

◆ UART2_BASE

#define UART2_BASE 0x44012004 /* UART_H1 */

◆ UART_BAUD_RATE_DIV_8

#define UART_BAUD_RATE_DIV_8 NO

◆ UART_BUS_MAX_NUMBER

#define UART_BUS_MAX_NUMBER 3

◆ ULP_AON_CTL_RB_ADDR

#define ULP_AON_CTL_RB_ADDR 0x5702c000

◆ ULP_GPIO0

#define ULP_GPIO0 107

◆ ULP_GPIO1

#define ULP_GPIO1 108

◆ ULP_GPIO2

#define ULP_GPIO2 109

◆ ULP_GPIO3

#define ULP_GPIO3 110

◆ ULP_GPIO_BASE_ADDR

#define ULP_GPIO_BASE_ADDR 0x57030000

◆ ULP_PIN

#define ULP_PIN SYS_RSTN

◆ USE_XIP_INDEX

#define USE_XIP_INDEX 1

◆ WATCHDOG_ROM_ENABLE

#define WATCHDOG_ROM_ENABLE YES

◆ XIP_CACHE_CTL

#define XIP_CACHE_CTL 0xA3006000

◆ XIP_EXIST

#define XIP_EXIST YES

◆ XIP_INT_BY_NMI

#define XIP_INT_BY_NMI YES

◆ XIP_WITH_OPI

#define XIP_WITH_OPI YES

◆ XO_CORE_CTRIM_REG

#define XO_CORE_CTRIM_REG 0x5702830c

◆ XO_CORE_TRIM_REG

#define XO_CORE_TRIM_REG 0x57028308

◆ YES

#define YES (1)

枚举类型说明

◆ i2c_bus_t

enum i2c_bus_t

I2C bus.

枚举值
I2C_BUS_0
I2C_BUS_1
I2C_BUS_NONE

◆ pin_t

enum pin_t

Definition of pin.

枚举值
GPIO_00
GPIO_01
GPIO_02
GPIO_03
GPIO_04
GPIO_05
GPIO_06
GPIO_07
GPIO_08
GPIO_09
GPIO_10
GPIO_11
GPIO_12
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
SFC_CLK
SFC_CSN
SFC_IO0
SFC_IO1
SFC_IO2
SFC_IO3
PIN_NONE

◆ qspi_bus_t

enum qspi_bus_t

枚举值
QSPI_BUS_0
QSPI_BUS_1
QSPI_BUS_NONE

◆ sio_bus_t

enum sio_bus_t

SIO(I2S/PCM) Bus.

枚举值
SIO_BUS_0
SIO_NONE

◆ slave_cpu_t

enum slave_cpu_t

枚举值
SLAVE_CPU_BT
SLAVE_CPU_MAX_NUM

◆ spi_bus_t

enum spi_bus_t

Definition of SPI bus index.

枚举值
SPI_BUS_0
SPI_BUS_1
SPI_BUS_2
SPI_BUS_3
SPI_BUS_4
SPI_BUS_5
SPI_BUS_6
SPI_BUS_NONE

◆ uart_bus_t

enum uart_bus_t

UART bus.

枚举值
UART_BUS_0
UART_BUS_1
UART_BUS_2
UART_BUS_NONE

函数说明

◆ get_hso_buff()

unsigned int get_hso_buff ( void )

extern