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hal_sio_v151_regs_op.h
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9#ifndef HAL_SIO_V151_REGS_OP_H
10#define HAL_SIO_V151_REGS_OP_H
11
12#include <stdint.h>
14#include "sio_porting.h"
15
16#ifdef __cplusplus
17#if __cplusplus
18extern "C" {
19#endif /* __cplusplus */
20#endif /* __cplusplus */
21
28#define sios_v151_regs(bus) ((sio_v151_regs_t *)g_hal_sio_regs[bus])
29
34
39
45static inline uint32_t hal_sio_v151_version_get_loop(sio_bus_t bus)
46{
48 version.d32 = sios_v151_regs(bus)->version;
49 return version.b.loop;
50}
51
57static inline void hal_sio_v151_version_set_loop(sio_bus_t bus, uint32_t val)
58{
60 version.d32 = sios_v151_regs(bus)->version;
61 version.b.loop = val;
62 sios_v151_regs(bus)->version = version.d32;
63}
64
70static inline uint32_t hal_sio_v151_mode_get_mode(sio_bus_t bus)
71{
73 mode.d32 = sios_v151_regs(bus)->mode;
74 return mode.b.mode;
75}
76
82static inline void hal_sio_v151_mode_set_mode(sio_bus_t bus, uint32_t val)
83{
85 mode.d32 = sios_v151_regs(bus)->mode;
86 mode.b.mode = val;
87 sios_v151_regs(bus)->mode = mode.d32;
88}
89
95static inline uint32_t hal_sio_v151_mode_get_pcm_mode(sio_bus_t bus)
96{
98 mode.d32 = sios_v151_regs(bus)->mode;
99 return mode.b.pcm_mode;
100}
101
107static inline void hal_sio_v151_mode_set_pcm_mode(sio_bus_t bus, uint32_t val)
108{
110 mode.d32 = sios_v151_regs(bus)->mode;
111 mode.b.pcm_mode = val;
112 sios_v151_regs(bus)->mode = mode.d32;
113}
114
120static inline uint32_t hal_sio_v151_mode_get_rxws_select(sio_bus_t bus)
121{
123 mode.d32 = sios_v151_regs(bus)->mode;
124 return mode.b.rxws_select;
125}
126
132static inline uint32_t hal_sio_v151_mode_get_ext_rec_en(sio_bus_t bus)
133{
135 mode.d32 = sios_v151_regs(bus)->mode;
136 return mode.b.ext_rec_en;
137}
138
144static inline void hal_sio_v151_mode_set_ext_rec_en(sio_bus_t bus, uint32_t val)
145{
147 mode.d32 = sios_v151_regs(bus)->mode;
148 mode.b.ext_rec_en = val;
149 sios_v151_regs(bus)->mode = mode.d32;
150}
151
157static inline uint32_t hal_sio_v151_mode_get_chn_num(sio_bus_t bus)
158{
160 mode.d32 = sios_v151_regs(bus)->mode;
161 return mode.b.chn_num;
162}
163
169static inline void hal_sio_v151_mode_set_chn_num(sio_bus_t bus, uint32_t val)
170{
172 mode.d32 = sios_v151_regs(bus)->mode;
173 mode.b.chn_num = val;
174 sios_v151_regs(bus)->mode = mode.d32;
175}
176
182static inline uint32_t hal_sio_v151_mode_get_clk_edge(sio_bus_t bus)
183{
185 mode.d32 = sios_v151_regs(bus)->mode;
186 return mode.b.clk_edge;
187}
188
194static inline void hal_sio_v151_mode_set_clk_edge(sio_bus_t bus, uint32_t val)
195{
197 mode.d32 = sios_v151_regs(bus)->mode;
198 mode.b.clk_edge = val;
199 sios_v151_regs(bus)->mode = mode.d32;
200}
201
207static inline uint32_t hal_sio_v151_mode_get_cfg_i2s_ms_mode_sel(sio_bus_t bus)
208{
210 mode.d32 = sios_v151_regs(bus)->mode;
211 return mode.b.cfg_i2s_ms_mode_sel;
212}
213
219static inline void hal_sio_v151_mode_set_cfg_i2s_ms_mode_sel(sio_bus_t bus, uint32_t val)
220{
222 mode.d32 = sios_v151_regs(bus)->mode;
223 mode.b.cfg_i2s_ms_mode_sel = val;
224 sios_v151_regs(bus)->mode = mode.d32;
225}
226
232static inline uint32_t hal_sio_v151_intstatus_get_rx_intr(sio_bus_t bus)
233{
235 intstatus.d32 = sios_v151_regs(bus)->intstatus;
236 return intstatus.b.rx_intr;
237}
238
244static inline uint32_t hal_sio_v151_intstatus_get_tx_intr(sio_bus_t bus)
245{
247 intstatus.d32 = sios_v151_regs(bus)->intstatus;
248 return intstatus.b.tx_intr;
249}
250
256static inline uint32_t hal_sio_v151_intstatus_get_rx_right_fifo_over(sio_bus_t bus)
257{
259 intstatus.d32 = sios_v151_regs(bus)->intstatus;
260 return intstatus.b.rx_right_fifo_over;
261}
262
268static inline uint32_t hal_sio_v151_intstatus_get_rx_left_fifo_over(sio_bus_t bus)
269{
271 intstatus.d32 = sios_v151_regs(bus)->intstatus;
272 return intstatus.b.rx_left_fifo_over;
273}
274
280static inline uint32_t hal_sio_v151_intstatus_get_tx_right_fifo_under(sio_bus_t bus)
281{
283 intstatus.d32 = sios_v151_regs(bus)->intstatus;
284 return intstatus.b.tx_right_fifo_under;
285}
286
292static inline uint32_t hal_sio_v151_intstatus_get_tx_left_fifo_under(sio_bus_t bus)
293{
295 intstatus.d32 = sios_v151_regs(bus)->intstatus;
296 return intstatus.b.tx_left_fifo_under;
297}
298
304static inline void hal_sio_v151_intclr_set_rx_intr(sio_bus_t bus, uint32_t val)
305{
307 intclr.d32 = sios_v151_regs(bus)->intclr;
308 intclr.b.rx_intr = val;
309 sios_v151_regs(bus)->intclr = intclr.d32;
310}
311
317static inline void hal_sio_v151_intclr_set_tx_intr(sio_bus_t bus, uint32_t val)
318{
320 intclr.d32 = sios_v151_regs(bus)->intclr;
321 intclr.b.tx_intr = val;
322 sios_v151_regs(bus)->intclr = intclr.d32;
323}
324
330static inline void hal_sio_v151_intclr_set_rx_right_fifo_over(sio_bus_t bus, uint32_t val)
331{
333 intclr.d32 = sios_v151_regs(bus)->intclr;
334 intclr.b.rx_right_fifo_over = val;
335 sios_v151_regs(bus)->intclr = intclr.d32;
336}
337
343static inline void hal_sio_v151_intclr_set_rx_left_fifo_over(sio_bus_t bus, uint32_t val)
344{
346 intclr.d32 = sios_v151_regs(bus)->intclr;
347 intclr.b.rx_left_fifo_over = val;
348 sios_v151_regs(bus)->intclr = intclr.d32;
349}
350
356static inline void hal_sio_v151_intclr_set_tx_right_fifo_under(sio_bus_t bus, uint32_t val)
357{
359 intclr.d32 = sios_v151_regs(bus)->intclr;
360 intclr.b.tx_right_fifo_under = val;
361 sios_v151_regs(bus)->intclr = intclr.d32;
362}
363
369static inline void hal_sio_v151_intclr_set_tx_left_fifo_under(sio_bus_t bus, uint32_t val)
370{
372 intclr.d32 = sios_v151_regs(bus)->intclr;
373 intclr.b.tx_left_fifo_under = val;
374 sios_v151_regs(bus)->intclr = intclr.d32;
375}
376
382static inline void hal_sio_v151_i2s_left_xd_set_tx_left_data(sio_bus_t bus, uint32_t val)
383{
384 sio_v151_i2s_left_xd_data_t i2s_left_xd;
385 i2s_left_xd.d32 = sios_v151_regs(bus)->left_tx;
386 i2s_left_xd.b.tx_left_data = val;
387 sios_v151_regs(bus)->left_tx = i2s_left_xd.d32;
388}
389
395static inline void hal_sio_v151_i2s_right_xd_set_tx_right_data(sio_bus_t bus, uint32_t val)
396{
397 sio_v151_i2s_right_xd_data_t i2s_right_xd;
398 i2s_right_xd.d32 = sios_v151_regs(bus)->right_tx;
399 i2s_right_xd.b.tx_right_data = val;
400 sios_v151_regs(bus)->right_tx = i2s_right_xd.d32;
401}
402
408static inline uint32_t hal_sio_v151_i2s_left_rd_get_rx_left_data(sio_bus_t bus)
409{
410 sio_v151_i2s_left_rd_data_t i2s_left_rd;
411 i2s_left_rd.d32 = sios_v151_regs(bus)->left_rx;
412 return i2s_left_rd.b.rx_left_data;
413}
414
420static inline uint32_t hal_sio_v151_i2s_right_rd_get_rx_right_data(sio_bus_t bus)
421{
422 sio_v151_i2s_right_rd_data_t i2s_right_rd;
423 i2s_right_rd.d32 = sios_v151_regs(bus)->right_rx;
424 return i2s_right_rd.b.rx_right_data;
425}
426
432static inline uint32_t hal_sio_v151_ct_set_get_tx_data_merge_en(sio_bus_t bus)
433{
435 ct_set.d32 = sios_v151_regs(bus)->ct_set;
436 return ct_set.b.tx_data_merge_en;
437}
438
444static inline void hal_sio_v151_ct_set_set_tx_data_merge_en(sio_bus_t bus, uint32_t val)
445{
447 ct_set.d32 = sios_v151_regs(bus)->ct_set;
448 ct_set.b.tx_data_merge_en = val;
449 sios_v151_regs(bus)->ct_set = ct_set.d32;
450}
451
457static inline uint32_t hal_sio_v151_ct_set_get_rx_data_merge_en(sio_bus_t bus)
458{
460 ct_set.d32 = sios_v151_regs(bus)->ct_set;
461 return ct_set.b.rx_data_merge_en;
462}
463
469static inline void hal_sio_v151_ct_set_set_rx_data_merge_en(sio_bus_t bus, uint32_t val)
470{
472 ct_set.d32 = sios_v151_regs(bus)->ct_set;
473 ct_set.b.rx_data_merge_en = val;
474 sios_v151_regs(bus)->ct_set = ct_set.d32;
475}
476
482static inline uint32_t hal_sio_v151_ct_set_get_tx_fifo_disable(sio_bus_t bus)
483{
485 ct_set.d32 = sios_v151_regs(bus)->ct_set;
486 return ct_set.b.tx_fifo_disable;
487}
488
494static inline void hal_sio_v151_ct_set_set_tx_fifo_disable(sio_bus_t bus, uint32_t val)
495{
497 ct_set.d32 = sios_v151_regs(bus)->ct_set;
498 ct_set.b.tx_fifo_disable = val;
499 sios_v151_regs(bus)->ct_set = ct_set.d32;
500}
501
507static inline uint32_t hal_sio_v151_ct_set_get_rx_fifo_disable(sio_bus_t bus)
508{
510 ct_set.d32 = sios_v151_regs(bus)->ct_set;
511 return ct_set.b.rx_fifo_disable;
512}
513
519static inline void hal_sio_v151_ct_set_set_rx_fifo_disable(sio_bus_t bus, uint32_t val)
520{
522 ct_set.d32 = sios_v151_regs(bus)->ct_set;
523 ct_set.b.rx_fifo_disable = val;
524 sios_v151_regs(bus)->ct_set = ct_set.d32;
525}
526
532static inline uint32_t hal_sio_v151_ct_set_get_tx_enable(sio_bus_t bus)
533{
535 ct_set.d32 = sios_v151_regs(bus)->ct_set;
536 return ct_set.b.tx_enable;
537}
538
544static inline void hal_sio_v151_ct_set_set_tx_enable(sio_bus_t bus, uint32_t val)
545{
547 ct_set.d32 = sios_v151_regs(bus)->ct_set;
548 ct_set.b.tx_enable = val;
549 sios_v151_regs(bus)->ct_set = ct_set.d32;
550}
551
557static inline uint32_t hal_sio_v151_ct_set_get_rx_enable(sio_bus_t bus)
558{
560 ct_set.d32 = sios_v151_regs(bus)->ct_set;
561 return ct_set.b.rx_enable;
562}
563
569static inline void hal_sio_v151_ct_set_set_rx_enable(sio_bus_t bus, uint32_t val)
570{
572 ct_set.d32 = sios_v151_regs(bus)->ct_set;
573 ct_set.b.rx_enable = val;
574 sios_v151_regs(bus)->ct_set = ct_set.d32;
575}
576
582static inline uint32_t hal_sio_v151_ct_set_get_intr_en(sio_bus_t bus)
583{
585 ct_set.d32 = sios_v151_regs(bus)->ct_set;
586 return ct_set.b.intr_en;
587}
588
594static inline void hal_sio_v151_ct_set_set_intr_en(sio_bus_t bus, uint32_t val)
595{
597 ct_set.d32 = sios_v151_regs(bus)->ct_set;
598 ct_set.b.intr_en = val;
599 sios_v151_regs(bus)->ct_set = ct_set.d32;
600}
601
607static inline uint32_t hal_sio_v151_ct_set_get_rst_n(sio_bus_t bus)
608{
610 ct_set.d32 = sios_v151_regs(bus)->ct_set;
611 return ct_set.b.rst_n;
612}
613
619static inline void hal_sio_v151_ct_set_set_rst_n(sio_bus_t bus, uint32_t val)
620{
622 ct_set.d32 = sios_v151_regs(bus)->ct_set;
623 ct_set.b.rst_n = val;
624 sios_v151_regs(bus)->ct_set = ct_set.d32;
625}
626
632static inline void hal_sio_v151_ct_clr_set_tx_data_merge_en(sio_bus_t bus, uint32_t val)
633{
635 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
636 ct_clr.b.tx_data_merge_en = val;
637 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
638}
639
645static inline uint32_t hal_sio_v151_ct_clr_get_rx_data_merge_en(sio_bus_t bus)
646{
648 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
649 return ct_clr.b.rx_data_merge_en;
650}
651
657static inline void hal_sio_v151_ct_clr_set_rx_data_merge_en(sio_bus_t bus, uint32_t val)
658{
660 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
661 ct_clr.b.rx_data_merge_en = val;
662 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
663}
664
670static inline uint32_t hal_sio_v151_ct_clr_get_tx_fifo_disable(sio_bus_t bus)
671{
673 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
674 return ct_clr.b.tx_fifo_disable;
675}
676
682static inline void hal_sio_v151_ct_clr_set_tx_fifo_disable(sio_bus_t bus, uint32_t val)
683{
685 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
686 ct_clr.b.tx_fifo_disable = val;
687 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
688}
689
695static inline uint32_t hal_sio_v151_ct_clr_get_rx_fifo_disable(sio_bus_t bus)
696{
698 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
699 return ct_clr.b.rx_fifo_disable;
700}
701
707static inline void hal_sio_v151_ct_clr_set_rx_fifo_disable(sio_bus_t bus, uint32_t val)
708{
710 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
711 ct_clr.b.rx_fifo_disable = val;
712 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
713}
714
720static inline uint32_t hal_sio_v151_ct_clr_get_tx_enable(sio_bus_t bus)
721{
723 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
724 return ct_clr.b.tx_enable;
725}
726
732static inline void hal_sio_v151_ct_clr_set_tx_enable(sio_bus_t bus, uint32_t val)
733{
735 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
736 ct_clr.b.tx_enable = val;
737 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
738}
739
745static inline uint32_t hal_sio_v151_ct_clr_get_rx_enable(sio_bus_t bus)
746{
748 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
749 return ct_clr.b.rx_enable;
750}
751
757static inline void hal_sio_v151_ct_clr_set_rx_enable(sio_bus_t bus, uint32_t val)
758{
760 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
761 ct_clr.b.rx_enable = val;
762 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
763}
764
770static inline void hal_sio_v151_ct_clr_set_intr_en(sio_bus_t bus, uint32_t val)
771{
773 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
774 ct_clr.b.intr_en = val;
775 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
776}
777
783static inline uint32_t hal_sio_v151_ct_clr_get_intr_en(sio_bus_t bus)
784{
786 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
787 return ct_clr.b.intr_en;
788}
789
795static inline void hal_sio_v151_ct_clr_set_rst_n(sio_bus_t bus, uint32_t val)
796{
798 ct_clr.d32 = sios_v151_regs(bus)->ct_clr;
799 ct_clr.b.rst_n = val;
800 sios_v151_regs(bus)->ct_clr = ct_clr.d32;
801}
802
808static inline uint32_t hal_sio_v151_fifo_threshold_get_rx_fifo_threshold(sio_bus_t bus)
809{
810 sio_v151_fifo_threshold_data_t fifo_threshold;
811 fifo_threshold.d32 = sios_v151_regs(bus)->fifo_threshold;
812 return fifo_threshold.b.rx_fifo_threshold;
813}
814
820static inline void hal_sio_v151_fifo_threshold_set_rx_fifo_threshold(sio_bus_t bus, uint32_t val)
821{
822 sio_v151_fifo_threshold_data_t fifo_threshold;
823 fifo_threshold.d32 = sios_v151_regs(bus)->fifo_threshold;
824 fifo_threshold.b.rx_fifo_threshold = val;
825 sios_v151_regs(bus)->fifo_threshold = fifo_threshold.d32;
826}
827
833static inline uint32_t hal_sio_v151_fifo_threshold_get_tx_fifo_threshold(sio_bus_t bus)
834{
835 sio_v151_fifo_threshold_data_t fifo_threshold;
836 fifo_threshold.d32 = sios_v151_regs(bus)->fifo_threshold;
837 return fifo_threshold.b.tx_fifo_threshold;
838}
839
845static inline void hal_sio_v151_fifo_threshold_set_tx_fifo_threshold(sio_bus_t bus, uint32_t val)
846{
847 sio_v151_fifo_threshold_data_t fifo_threshold;
848 fifo_threshold.d32 = sios_v151_regs(bus)->fifo_threshold;
849 fifo_threshold.b.tx_fifo_threshold = val;
850 sios_v151_regs(bus)->fifo_threshold = fifo_threshold.d32;
851}
852
858static inline uint32_t hal_sio_v151_rx_sta_get_rx_left_depth(sio_bus_t bus)
859{
861 rx_sta.d32 = sios_v151_regs(bus)->rx_sta;
862 return rx_sta.b.rx_left_depth;
863}
864
870static inline uint32_t hal_sio_v151_rx_sta_get_rx_right_depth(sio_bus_t bus)
871{
873 rx_sta.d32 = sios_v151_regs(bus)->rx_sta;
874 return rx_sta.b.rx_right_depth;
875}
876
882static inline uint32_t hal_sio_v151_tx_sta_get_tx_left_depth(sio_bus_t bus)
883{
885 tx_sta.d32 = sios_v151_regs(bus)->tx_sta;
886 return tx_sta.b.tx_left_depth;
887}
888
894static inline void hal_sio_v151_tx_sta_set_tx_left_depth(sio_bus_t bus, uint32_t val)
895{
897 tx_sta.d32 = sios_v151_regs(bus)->tx_sta;
898 tx_sta.b.tx_left_depth = val;
899 sios_v151_regs(bus)->tx_sta = tx_sta.d32;
900}
901
907static inline uint32_t hal_sio_v151_tx_sta_get_tx_right_depth(sio_bus_t bus)
908{
910 tx_sta.d32 = sios_v151_regs(bus)->tx_sta;
911 return tx_sta.b.tx_right_depth;
912}
913
919static inline void hal_sio_v151_tx_sta_set_tx_right_depth(sio_bus_t bus, uint32_t val)
920{
922 tx_sta.d32 = sios_v151_regs(bus)->tx_sta;
923 tx_sta.b.tx_right_depth = val;
924 sios_v151_regs(bus)->tx_sta = tx_sta.d32;
925}
926
932static inline uint32_t hal_sio_v151_data_width_get_tx_mode(sio_bus_t bus)
933{
934 sio_v151_data_width_set_data_t data_width_set;
935 data_width_set.d32 = sios_v151_regs(bus)->data_width_set;
936 return data_width_set.b.tx_mode;
937}
938
944static inline void hal_sio_v151_data_width_set_tx_mode(sio_bus_t bus, uint32_t val)
945{
946 sio_v151_data_width_set_data_t data_width_set;
947 data_width_set.d32 = sios_v151_regs(bus)->data_width_set;
948 data_width_set.b.tx_mode = val;
949 sios_v151_regs(bus)->data_width_set = data_width_set.d32;
950}
951
957static inline uint32_t hal_sio_v151_data_width_get_rx_mode(sio_bus_t bus)
958{
959 sio_v151_data_width_set_data_t data_width_set;
960 data_width_set.d32 = sios_v151_regs(bus)->data_width_set;
961 return data_width_set.b.rx_mode;
962}
963
969static inline void hal_sio_v151_data_width_set_rx_mode(sio_bus_t bus, uint32_t val)
970{
971 sio_v151_data_width_set_data_t data_width_set;
972 data_width_set.d32 = sios_v151_regs(bus)->data_width_set;
973 data_width_set.b.rx_mode = val;
974 sios_v151_regs(bus)->data_width_set = data_width_set.d32;
975}
976
982static inline uint32_t hal_sio_v151_start_pos_get_read(sio_bus_t bus)
983{
985 start_pos.d32 = sios_v151_regs(bus)->i2s_start_pos;
986 return start_pos.b.start_post_read;
987}
988
994static inline void hal_sio_v151_start_pos_set_read(sio_bus_t bus, uint32_t val)
995{
997 start_pos.d32 = sios_v151_regs(bus)->i2s_start_pos;
998 start_pos.b.start_post_read = val;
999 sios_v151_regs(bus)->i2s_start_pos = start_pos.d32;
1000}
1001
1007static inline uint32_t hal_sio_v151_start_pos_get_write(sio_bus_t bus)
1008{
1010 start_pos.d32 = sios_v151_regs(bus)->i2s_start_pos;
1011 return start_pos.b.start_pos_write;
1012}
1013
1019static inline void hal_sio_v151_start_pos_set_write(sio_bus_t bus, uint32_t val)
1020{
1022 start_pos.d32 = sios_v151_regs(bus)->i2s_start_pos;
1023 start_pos.b.start_pos_write = val;
1024 sios_v151_regs(bus)->i2s_start_pos = start_pos.d32;
1025}
1026
1032static inline uint32_t hal_sio_v151_pos_flag_get_read(sio_bus_t bus)
1033{
1034 sio_v151_pos_flag_data_t pos_flag;
1035 pos_flag.d32 = sios_v151_regs(bus)->i2s_pos_flag;
1036 return pos_flag.b.start_post_read;
1037}
1038
1044static inline void hal_sio_v151_pos_flag_set_read(sio_bus_t bus, uint32_t val)
1045{
1046 sio_v151_pos_flag_data_t pos_flag;
1047 pos_flag.d32 = sios_v151_regs(bus)->i2s_pos_flag;
1048 pos_flag.b.start_post_read = val;
1049 sios_v151_regs(bus)->i2s_pos_flag = pos_flag.d32;
1050}
1051
1057static inline uint32_t hal_sio_v151_pos_flag_get_write(sio_bus_t bus)
1058{
1059 sio_v151_pos_flag_data_t pos_flag;
1060 pos_flag.d32 = sios_v151_regs(bus)->i2s_pos_flag;
1061 return pos_flag.b.start_pos_write;
1062}
1063
1069static inline void hal_sio_v151_pos_flag_set_write(sio_bus_t bus, uint32_t val)
1070{
1071 sio_v151_pos_flag_data_t pos_flag;
1072 pos_flag.d32 = sios_v151_regs(bus)->i2s_pos_flag;
1073 pos_flag.b.start_pos_write = val;
1074 sios_v151_regs(bus)->i2s_pos_flag = pos_flag.d32;
1075}
1076
1082static inline uint32_t hal_sio_v151_signed_ext_get_en(sio_bus_t bus)
1083{
1084 sio_v151_signed_ext_data_t signed_ext;
1085 signed_ext.d32 = sios_v151_regs(bus)->signed_ext;
1086 return signed_ext.b.signed_ext_en;
1087}
1088
1094static inline void hal_sio_v151_signed_ext_set_en(sio_bus_t bus, uint32_t val)
1095{
1096 sio_v151_signed_ext_data_t signed_ext;
1097 signed_ext.d32 = sios_v151_regs(bus)->signed_ext;
1098 signed_ext.b.signed_ext_en = val;
1099 sios_v151_regs(bus)->signed_ext = signed_ext.d32;
1100}
1101
1107static inline uint32_t hal_sio_v151_pos_merge_get_en(sio_bus_t bus)
1108{
1110 pos_merge.d32 = sios_v151_regs(bus)->i2s_pos_merge_en;
1111 return pos_merge.b.merge_en;
1112}
1113
1119static inline void hal_sio_v151_pos_merge_set_en(sio_bus_t bus, uint32_t val)
1120{
1122 pos_merge.d32 = sios_v151_regs(bus)->i2s_pos_merge_en;
1123 pos_merge.b.merge_en = val;
1124 sios_v151_regs(bus)->i2s_pos_merge_en = pos_merge.d32;
1125}
1126
1132static inline uint32_t hal_sio_v151_i2s_crg_get_bclk_div_en(sio_bus_t bus)
1133{
1135 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1136 return i2s_crg.b.i2s_bclk_div_en;
1137}
1138
1144static inline void hal_sio_v151_i2s_crg_set_bclk_div_en(sio_bus_t bus, uint32_t val)
1145{
1147 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1148 i2s_crg.b.i2s_bclk_div_en = val;
1149 sios_v151_regs(bus)->i2s_crg = i2s_crg.d32;
1150}
1151
1157static inline uint32_t hal_sio_v151_i2s_crg_get_crg_clken(sio_bus_t bus)
1158{
1160 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1161 return i2s_crg.b.i2s_crg_clken;
1162}
1163
1169static inline void hal_sio_v151_i2s_crg_set_crg_clken(sio_bus_t bus, uint32_t val)
1170{
1172 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1173 i2s_crg.b.i2s_crg_clken = val;
1174 sios_v151_regs(bus)->i2s_crg = i2s_crg.d32;
1175}
1176
1182static inline uint32_t hal_sio_v151_i2s_crg_get_bclk_sel(sio_bus_t bus)
1183{
1185 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1186 return i2s_crg.b.i2s_bclk_sel;
1187}
1188
1194static inline void hal_sio_v151_i2s_crg_set_bclk_sel(sio_bus_t bus, uint32_t val)
1195{
1197 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1198 i2s_crg.b.i2s_bclk_sel = val;
1199 sios_v151_regs(bus)->i2s_crg = i2s_crg.d32;
1200}
1201
1207static inline uint32_t hal_sio_v151_i2s_crg_get_fs_sel(sio_bus_t bus)
1208{
1210 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1211 return i2s_crg.b.i2s_fs_sel;
1212}
1213
1219static inline void hal_sio_v151_i2s_crg_set_fs_sel(sio_bus_t bus, uint32_t val)
1220{
1222 i2s_crg.d32 = sios_v151_regs(bus)->i2s_crg;
1223 i2s_crg.b.i2s_fs_sel = val;
1224 sios_v151_regs(bus)->i2s_crg = i2s_crg.d32;
1225}
1226
1232static inline uint32_t hal_sio_v151_bclk_div_num_get_num(sio_bus_t bus)
1233{
1235 i2s_bclk.d32 = sios_v151_regs(bus)->i2s_bclk_div_num;
1236 return i2s_bclk.b.bclk_div_num;
1237}
1238
1244static inline void hal_sio_v151_bclk_div_num_set_num(sio_bus_t bus, uint32_t val)
1245{
1247 i2s_bclk.d32 = sios_v151_regs(bus)->i2s_bclk_div_num;
1248 i2s_bclk.b.bclk_div_num = val;
1249 sios_v151_regs(bus)->i2s_bclk_div_num = i2s_bclk.d32;
1250}
1251
1257static inline uint32_t hal_sio_v151_fs_div_num_get_num(sio_bus_t bus)
1258{
1260 i2s_fs.d32 = sios_v151_regs(bus)->i2s_fs_div_num;
1261 return i2s_fs.b.fs_div_num;
1262}
1263
1269static inline void hal_sio_v151_fs_div_num_set_num(sio_bus_t bus, uint32_t val)
1270{
1272 i2s_fs.d32 = sios_v151_regs(bus)->i2s_fs_div_num;
1273 i2s_fs.b.fs_div_num = val;
1274 sios_v151_regs(bus)->i2s_fs_div_num = i2s_fs.d32;
1275}
1276
1282static inline uint32_t hal_sio_v151_fs_div_ratio_num_get_num(sio_bus_t bus)
1283{
1285 i2s_fs.d32 = sios_v151_regs(bus)->i2s_fs_div_ratio_num;
1286 return i2s_fs.b.fs_div_ratio_num;
1287}
1288
1294static inline void hal_sio_v151_fs_div_ratio_num_set_num(sio_bus_t bus, uint32_t val)
1295{
1297 i2s_fs.d32 = sios_v151_regs(bus)->i2s_fs_div_ratio_num;
1298 i2s_fs.b.fs_div_ratio_num = val;
1299 sios_v151_regs(bus)->i2s_fs_div_ratio_num = i2s_fs.d32;
1300}
1301
1302static inline void hal_sio_fifo_threshold_set_tx_fifo_threshold(sio_bus_t bus, uint32_t val)
1303{
1304 uint32_t threshold = sios_v151_regs(bus)->fifo_threshold;
1305 threshold = (threshold & 0xff00);
1306 threshold = (threshold | (val & 0xff));
1307 sios_v151_regs(bus)->fifo_threshold = threshold;
1308}
1309
1310#define SIO_RX_FIFO_SHIFT_MASK 8
1311
1312static inline void hal_sio_fifo_threshold_set_rx_fifo_threshold(sio_bus_t bus, uint32_t val)
1313{
1314 uint32_t threshold = sios_v151_regs(bus)->fifo_threshold;
1315 threshold = (threshold & 0xff);
1316 threshold = (threshold | ((val & 0xff) << SIO_RX_FIFO_SHIFT_MASK));
1317 sios_v151_regs(bus)->fifo_threshold = threshold;
1318}
1319
1320static inline void hal_sio_set_intmask(sio_bus_t bus, uint32_t mask)
1321{
1322 sios_v151_regs(bus)->intmask = mask;
1323}
1324
1325static inline uint32_t hal_sio_get_merge_rx_data(sio_bus_t bus)
1326{
1327 uint32_t i2s_rd;
1328 i2s_rd = sios_v151_regs(bus)->i2s_dual_rx_chn;
1329 return i2s_rd;
1330}
1331
1336#ifdef __cplusplus
1337#if __cplusplus
1338}
1339#endif /* __cplusplus */
1340#endif /* __cplusplus */
1341
1342#endif
sio_bus_t
SIO(I2S/PCM) Bus.
Definition platform_core.h:254
#define I2S_MAX_NUMBER
Definition platform_core.h:138
void hal_sio_v151_regs_init(sio_bus_t bus)
Init the sio which will set the base address of registers.
#define sios_v151_regs(bus)
Definition hal_sio_v151_regs_op.h:28
uintptr_t g_hal_sio_regs[I2S_MAX_NUMBER]
Definition hal_sio.c:12
#define SIO_RX_FIFO_SHIFT_MASK
Definition hal_sio_v151_regs_op.h:1310
void hal_sio_v151_regs_deinit(sio_bus_t bus)
Deinit the sio which will clear the base address of registers.
unsigned int uintptr_t
Definition td_type.h:65
This union represents the bit fields in the sio_ct_clr register. Read the register into the d32 membe...
Definition hal_sio_v151_regs_def.h:197
uint32_t rx_enable
Definition hal_sio_v151_regs_def.h:217
struct sio_v151_ct_clr_data::@294 b
uint32_t tx_enable
Definition hal_sio_v151_regs_def.h:214
uint32_t rx_data_merge_en
Definition hal_sio_v151_regs_def.h:205
uint32_t intr_en
Definition hal_sio_v151_regs_def.h:220
uint32_t tx_data_merge_en
Definition hal_sio_v151_regs_def.h:202
uint32_t tx_fifo_disable
Definition hal_sio_v151_regs_def.h:208
uint32_t d32
Definition hal_sio_v151_regs_def.h:198
uint32_t rst_n
Definition hal_sio_v151_regs_def.h:223
uint32_t rx_fifo_disable
Definition hal_sio_v151_regs_def.h:211
This union represents the bit fields in the sio_ct_set register. Read the register into the d32 membe...
Definition hal_sio_v151_regs_def.h:161
uint32_t intr_en
Definition hal_sio_v151_regs_def.h:184
uint32_t tx_enable
Definition hal_sio_v151_regs_def.h:178
uint32_t d32
Definition hal_sio_v151_regs_def.h:162
uint32_t rx_fifo_disable
Definition hal_sio_v151_regs_def.h:175
uint32_t tx_data_merge_en
Definition hal_sio_v151_regs_def.h:166
uint32_t tx_fifo_disable
Definition hal_sio_v151_regs_def.h:172
uint32_t rst_n
Definition hal_sio_v151_regs_def.h:187
uint32_t rx_data_merge_en
Definition hal_sio_v151_regs_def.h:169
struct sio_v151_ct_set_data::@293 b
uint32_t rx_enable
Definition hal_sio_v151_regs_def.h:181
This union represents the bit fields in the sio_data_width_set register. Read the register into the d...
Definition hal_sio_v151_regs_def.h:275
uint32_t rx_mode
Definition hal_sio_v151_regs_def.h:279
uint32_t d32
Definition hal_sio_v151_regs_def.h:276
uint32_t tx_mode
Definition hal_sio_v151_regs_def.h:278
struct sio_v151_data_width_set_data::@298 b
This union represents the bit fields in the sio_fifo_threshold register. Read the register into the d...
Definition hal_sio_v151_regs_def.h:233
uint32_t rx_fifo_threshold
Definition hal_sio_v151_regs_def.h:237
uint32_t d32
Definition hal_sio_v151_regs_def.h:234
uint32_t tx_fifo_threshold
Definition hal_sio_v151_regs_def.h:236
struct sio_v151_fifo_threshold_data::@295 b
This union represents the bit fields in the cfg_i2s_bclk_div_num register. Read the register into the...
Definition hal_sio_v151_regs_def.h:402
uint32_t bclk_div_num
Definition hal_sio_v151_regs_def.h:405
uint32_t d32
Definition hal_sio_v151_regs_def.h:403
struct sio_v151_i2s_bclk_div_num_data::@305 b
This union represents the bit fields in the cfg_i2s_crg register. Read the register into the d32 memb...
Definition hal_sio_v151_regs_def.h:385
struct sio_v151_i2s_crg_data::@304 b
uint32_t i2s_bclk_div_en
Definition hal_sio_v151_regs_def.h:388
uint32_t i2s_bclk_sel
Definition hal_sio_v151_regs_def.h:390
uint32_t d32
Definition hal_sio_v151_regs_def.h:386
uint32_t i2s_crg_clken
Definition hal_sio_v151_regs_def.h:389
uint32_t i2s_fs_sel
Definition hal_sio_v151_regs_def.h:392
This union represents the bit fields in the cfg_i2s_fs_div_num register. Read the register into the d...
Definition hal_sio_v151_regs_def.h:415
uint32_t d32
Definition hal_sio_v151_regs_def.h:416
uint32_t fs_div_num
Definition hal_sio_v151_regs_def.h:418
struct sio_v151_i2s_fs_div_num_data::@306 b
This union represents the bit fields in the cfg_i2s_fs_div_num register. Read the register into the d...
Definition hal_sio_v151_regs_def.h:428
uint32_t fs_div_ratio_num
Definition hal_sio_v151_regs_def.h:431
struct sio_v151_i2s_fs_div_ratio_num_data::@307 b
uint32_t d32
Definition hal_sio_v151_regs_def.h:429
This union represents the bit fields in the sio_i2s_left_rd register. Read the register into the d32 ...
Definition hal_sio_v151_regs_def.h:138
uint32_t d32
Definition hal_sio_v151_regs_def.h:139
struct sio_v151_i2s_left_rd_data::@291 b
uint32_t rx_left_data
Definition hal_sio_v151_regs_def.h:141
This union represents the bit fields in the sio_i2s_left_xd register. Read the register into the d32 ...
Definition hal_sio_v151_regs_def.h:114
uint32_t d32
Definition hal_sio_v151_regs_def.h:115
struct sio_v151_i2s_left_xd_data::@289 b
uint32_t tx_left_data
Definition hal_sio_v151_regs_def.h:117
This union represents the bit fields in the sio_i2s_pos_merge_en register. Read the register into the...
Definition hal_sio_v151_regs_def.h:340
uint32_t d32
Definition hal_sio_v151_regs_def.h:341
uint32_t merge_en
Definition hal_sio_v151_regs_def.h:343
struct sio_v151_i2s_pos_merge_en_data::@302 b
This union represents the bit fields in the sio_i2s_right_xd register. Read the register into the d32...
Definition hal_sio_v151_regs_def.h:150
uint32_t d32
Definition hal_sio_v151_regs_def.h:151
struct sio_v151_i2s_right_rd_data::@292 b
uint32_t rx_right_data
Definition hal_sio_v151_regs_def.h:153
This union represents the bit fields in the sio_i2s_right_xd register. Read the register into the d32...
Definition hal_sio_v151_regs_def.h:126
struct sio_v151_i2s_right_xd_data::@290 b
uint32_t tx_right_data
Definition hal_sio_v151_regs_def.h:129
uint32_t d32
Definition hal_sio_v151_regs_def.h:127
This union represents the bit fields in the sio_i2s_start_pos register. Read the register into the d3...
Definition hal_sio_v151_regs_def.h:289
uint32_t d32
Definition hal_sio_v151_regs_def.h:290
uint32_t start_post_read
Definition hal_sio_v151_regs_def.h:292
uint32_t start_pos_write
Definition hal_sio_v151_regs_def.h:295
struct sio_v151_i2s_start_pos_data::@299 b
This union represents the bit fields in the sio_intclr register. Read the register into the d32 membe...
Definition hal_sio_v151_regs_def.h:96
uint32_t tx_intr
Definition hal_sio_v151_regs_def.h:100
uint32_t rx_intr
Definition hal_sio_v151_regs_def.h:99
uint32_t d32
Definition hal_sio_v151_regs_def.h:97
uint32_t rx_right_fifo_over
Definition hal_sio_v151_regs_def.h:101
uint32_t tx_left_fifo_under
Definition hal_sio_v151_regs_def.h:104
uint32_t tx_right_fifo_under
Definition hal_sio_v151_regs_def.h:103
struct sio_v151_intclr_data::@288 b
uint32_t rx_left_fifo_over
Definition hal_sio_v151_regs_def.h:102
This union represents the bit fields in the sio_intstatus register. Read the register into the d32 me...
Definition hal_sio_v151_regs_def.h:78
uint32_t rx_left_fifo_over
Definition hal_sio_v151_regs_def.h:84
uint32_t tx_intr
Definition hal_sio_v151_regs_def.h:82
uint32_t rx_intr
Definition hal_sio_v151_regs_def.h:81
uint32_t d32
Definition hal_sio_v151_regs_def.h:79
uint32_t tx_left_fifo_under
Definition hal_sio_v151_regs_def.h:86
struct sio_v151_intstatus_data::@287 b
uint32_t tx_right_fifo_under
Definition hal_sio_v151_regs_def.h:85
uint32_t rx_right_fifo_over
Definition hal_sio_v151_regs_def.h:83
This union represents the bit fields in the sio_mode register. Read the register into the d32 member ...
Definition hal_sio_v151_regs_def.h:47
uint32_t cfg_i2s_ms_mode_sel
Definition hal_sio_v151_regs_def.h:68
uint32_t mode
Definition hal_sio_v151_regs_def.h:50
uint32_t clk_edge
Definition hal_sio_v151_regs_def.h:65
struct sio_v151_mode_data::@286 b
uint32_t pcm_mode
Definition hal_sio_v151_regs_def.h:53
uint32_t d32
Definition hal_sio_v151_regs_def.h:48
uint32_t chn_num
Definition hal_sio_v151_regs_def.h:60
uint32_t rxws_select
Definition hal_sio_v151_regs_def.h:56
uint32_t ext_rec_en
Definition hal_sio_v151_regs_def.h:57
This union represents the bit fields in the sio_pos_flag register. Read the register into the d32 mem...
Definition hal_sio_v151_regs_def.h:307
uint32_t d32
Definition hal_sio_v151_regs_def.h:308
struct sio_v151_pos_flag_data::@300 b
uint32_t start_post_read
Definition hal_sio_v151_regs_def.h:310
uint32_t start_pos_write
Definition hal_sio_v151_regs_def.h:313
This union represents the bit fields in the sio_rx_sta register. Read the register into the d32 membe...
Definition hal_sio_v151_regs_def.h:247
uint32_t rx_left_depth
Definition hal_sio_v151_regs_def.h:250
uint32_t rx_right_depth
Definition hal_sio_v151_regs_def.h:251
struct sio_v151_rx_sta_data::@296 b
uint32_t d32
Definition hal_sio_v151_regs_def.h:248
This union represents the bit fields in the sio_signed_ext register. Read the register into the d32 m...
Definition hal_sio_v151_regs_def.h:325
struct sio_v151_signed_ext_data::@301 b
uint32_t d32
Definition hal_sio_v151_regs_def.h:326
uint32_t signed_ext_en
Definition hal_sio_v151_regs_def.h:328
This union represents the bit fields in the sio_tx_sta register. Read the register into the d32 membe...
Definition hal_sio_v151_regs_def.h:261
uint32_t d32
Definition hal_sio_v151_regs_def.h:262
uint32_t tx_left_depth
Definition hal_sio_v151_regs_def.h:264
uint32_t tx_right_depth
Definition hal_sio_v151_regs_def.h:265
struct sio_v151_tx_sta_data::@297 b
This union represents the bit fields in the sio_version register. Read the register into the d32 memb...
Definition hal_sio_v151_regs_def.h:31
uint32_t d32
Definition hal_sio_v151_regs_def.h:32
struct sio_v151_version_data::@285 b
uint32_t loop
Definition hal_sio_v151_regs_def.h:35