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hal_sio_v150_regs_op.h
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1
9#ifndef HAL_SIO_V150_REGS_OP_H
10#define HAL_SIO_V150_REGS_OP_H
11
12#include <stdint.h>
14#include "sio_porting.h"
15
16#ifdef __cplusplus
17#if __cplusplus
18extern "C" {
19#endif /* __cplusplus */
20#endif /* __cplusplus */
21
29#define sios_v150_regs(bus) ((sio_v150_regs_t *)g_hal_sio_regs[bus])
30
35
36
37static inline void hal_sio_v150_pos_merge_set_en(sio_bus_t bus, uint32_t val)
38{
39 sio_v150_i2s_pos_merge_en_data_t pos_merge = {.d32 = sios_v150_regs(bus)->i2s_pos_merge_en};
40 pos_merge.b.merge_en = val;
41 sios_v150_regs(bus)->i2s_pos_merge_en = pos_merge.d32;
42}
43
49
55void hal_sio_v150_ct_set_set_rx_enable(sio_bus_t bus, uint32_t val);
56
62void hal_sio_v150_ct_set_set_tx_enable(sio_bus_t bus, uint32_t val);
63
69static inline uint32_t hal_sio_v150_version_get_loop(sio_bus_t bus)
70{
72 version.d32 = sios_v150_regs(bus)->version;
73 return version.b.loop;
74}
75
81static inline void hal_sio_v150_version_set_loop(sio_bus_t bus, uint32_t val)
82{
83 sio_v150_version_data_t version = {.d32 = sios_v150_regs(bus)->version};
84 version.b.loop = val;
85 sios_v150_regs(bus)->version = version.d32;
86}
87
93static inline uint32_t hal_sio_v150_mode_get_mode(sio_bus_t bus)
94{
96 mode.d32 = sios_v150_regs(bus)->mode;
97 return mode.b.mode;
98}
99
105static inline void hal_sio_v150_mode_set_mode(sio_bus_t bus, uint32_t val)
106{
108 mode.d32 = sios_v150_regs(bus)->mode;
109 mode.b.mode = val;
110 sios_v150_regs(bus)->mode = mode.d32;
111}
112
118static inline uint32_t hal_sio_v150_mode_get_pcm_mode(sio_bus_t bus)
119{
121 mode.d32 = sios_v150_regs(bus)->mode;
122 return mode.b.pcm_mode;
123}
124
130static inline void hal_sio_v150_mode_set_pcm_mode(sio_bus_t bus, uint32_t val)
131{
133 mode.d32 = sios_v150_regs(bus)->mode;
134 mode.b.pcm_mode = val;
135 sios_v150_regs(bus)->mode = mode.d32;
136}
137
143static inline uint32_t hal_sio_v150_mode_get_ext_rec_en(sio_bus_t bus)
144{
146 mode.d32 = sios_v150_regs(bus)->mode;
147 return mode.b.ext_rec_en;
148}
149
155static inline void hal_sio_v150_mode_set_ext_rec_en(sio_bus_t bus, uint32_t val)
156{
158 mode.d32 = sios_v150_regs(bus)->mode;
159 mode.b.ext_rec_en = val;
160 sios_v150_regs(bus)->mode = mode.d32;
161}
162
168static inline uint32_t hal_sio_v150_mode_get_chn_num(sio_bus_t bus)
169{
171 mode.d32 = sios_v150_regs(bus)->mode;
172 return mode.b.chn_num;
173}
174
180static inline void hal_sio_v150_mode_set_chn_num(sio_bus_t bus, uint32_t val)
181{
183 mode.d32 = sios_v150_regs(bus)->mode;
184 mode.b.chn_num = val;
185 sios_v150_regs(bus)->mode = mode.d32;
186}
187
193static inline uint32_t hal_sio_v150_mode_get_clk_edge(sio_bus_t bus)
194{
196 mode.d32 = sios_v150_regs(bus)->mode;
197 return mode.b.clk_edge;
198}
199
205static inline void hal_sio_v150_mode_set_clk_edge(sio_bus_t bus, uint32_t val)
206{
208 mode.d32 = sios_v150_regs(bus)->mode;
209 mode.b.clk_edge = val;
210 sios_v150_regs(bus)->mode = mode.d32;
211}
212
218static inline uint32_t hal_sio_v150_intstatus_get_rx_intr(sio_bus_t bus)
219{
221 intstatus.d32 = sios_v150_regs(bus)->intstatus;
222 return intstatus.b.rx_intr;
223}
224
230static inline uint32_t hal_sio_v150_intstatus_get_tx_intr(sio_bus_t bus)
231{
233 intstatus.d32 = sios_v150_regs(bus)->intstatus;
234 return intstatus.b.tx_intr;
235}
236
242static inline uint32_t hal_sio_v150_intstatus_get_rx_right_fifo_over(sio_bus_t bus)
243{
245 intstatus.d32 = sios_v150_regs(bus)->intstatus;
246 return intstatus.b.rx_right_fifo_over;
247}
248
254static inline uint32_t hal_sio_v150_intstatus_get_rx_left_fifo_over(sio_bus_t bus)
255{
257 intstatus.d32 = sios_v150_regs(bus)->intstatus;
258 return intstatus.b.rx_left_fifo_over;
259}
260
266static inline uint32_t hal_sio_v150_intstatus_get_tx_right_fifo_under(sio_bus_t bus)
267{
269 intstatus.d32 = sios_v150_regs(bus)->intstatus;
270 return intstatus.b.tx_right_fifo_under;
271}
272
278static inline uint32_t hal_sio_v150_intstatus_get_tx_left_fifo_under(sio_bus_t bus)
279{
281 intstatus.d32 = sios_v150_regs(bus)->intstatus;
282 return intstatus.b.tx_left_fifo_under;
283}
284
290static inline void hal_sio_v150_intclr_set_rx_intr(sio_bus_t bus, uint32_t val)
291{
293 intclr.d32 = sios_v150_regs(bus)->intclr;
294 intclr.b.rx_intr = val;
295 sios_v150_regs(bus)->intclr = intclr.d32;
296}
297
303static inline void hal_sio_v150_intclr_set_tx_intr(sio_bus_t bus, uint32_t val)
304{
306 intclr.d32 = sios_v150_regs(bus)->intclr;
307 intclr.b.tx_intr = val;
308 sios_v150_regs(bus)->intclr = intclr.d32;
309}
310
316static inline void hal_sio_v150_intclr_set_rx_right_fifo_over(sio_bus_t bus, uint32_t val)
317{
319 intclr.d32 = sios_v150_regs(bus)->intclr;
320 intclr.b.rx_right_fifo_over = val;
321 sios_v150_regs(bus)->intclr = intclr.d32;
322}
323
329static inline void hal_sio_v150_intclr_set_rx_left_fifo_over(sio_bus_t bus, uint32_t val)
330{
332 intclr.d32 = sios_v150_regs(bus)->intclr;
333 intclr.b.rx_left_fifo_over = val;
334 sios_v150_regs(bus)->intclr = intclr.d32;
335}
336
342static inline void hal_sio_v150_intclr_set_tx_right_fifo_under(sio_bus_t bus, uint32_t val)
343{
345 intclr.d32 = sios_v150_regs(bus)->intclr;
346 intclr.b.tx_right_fifo_under = val;
347 sios_v150_regs(bus)->intclr = intclr.d32;
348}
349
355static inline void hal_sio_v150_intclr_set_tx_left_fifo_under(sio_bus_t bus, uint32_t val)
356{
358 intclr.d32 = sios_v150_regs(bus)->intclr;
359 intclr.b.tx_left_fifo_under = val;
360 sios_v150_regs(bus)->intclr = intclr.d32;
361}
362
368static inline void hal_sio_v150_left_tx_set_data(sio_bus_t bus, uint32_t val)
369{
371 left_tx.d32 = sios_v150_regs(bus)->left_tx;
372 left_tx.b.data = val;
373 sios_v150_regs(bus)->left_tx = left_tx.d32;
374}
375
381static inline void hal_sio_v150_right_tx_set_data(sio_bus_t bus, uint32_t val)
382{
384 right_tx.d32 = sios_v150_regs(bus)->right_tx;
385 right_tx.b.data = val;
386 sios_v150_regs(bus)->right_tx = right_tx.d32;
387}
388
394static inline uint32_t hal_sio_v150_left_rx_get_data(sio_bus_t bus)
395{
397 left_rx.d32 = sios_v150_regs(bus)->left_rx;
398 return left_rx.b.data;
399}
400
406static inline uint32_t hal_sio_v150_right_rx_get_data(sio_bus_t bus)
407{
409 right_rx.d32 = sios_v150_regs(bus)->right_rx;
410 return right_rx.b.data;
411}
412
418static inline uint32_t hal_sio_v150_ct_set_get_tx_fifo_threshold(sio_bus_t bus)
419{
421 ct_set.d32 = sios_v150_regs(bus)->ct_set;
422 return ct_set.b.tx_fifo_threshold;
423}
424
430static inline void hal_sio_v150_ct_set_set_tx_fifo_threshold(sio_bus_t bus, uint32_t val)
431{
433 ct_set.d32 = sios_v150_regs(bus)->ct_set;
434 ct_set.b.tx_fifo_threshold = val;
435 sios_v150_regs(bus)->ct_set = ct_set.d32;
436}
437
443static inline uint32_t hal_sio_v150_ct_set_get_rx_fifo_threshold(sio_bus_t bus)
444{
446 ct_set.d32 = sios_v150_regs(bus)->ct_set;
447 return ct_set.b.rx_fifo_threshold;
448}
449
455static inline void hal_sio_v150_ct_set_set_rx_fifo_threshold(sio_bus_t bus, uint32_t val)
456{
458 ct_set.d32 = sios_v150_regs(bus)->ct_set;
459 ct_set.b.rx_fifo_threshold = val;
460 sios_v150_regs(bus)->ct_set = ct_set.d32;
461}
462
468static inline uint32_t hal_sio_v150_ct_set_get_tx_data_merge_en(sio_bus_t bus)
469{
471 ct_set.d32 = sios_v150_regs(bus)->ct_set;
472 return ct_set.b.tx_data_merge_en;
473}
474
480static inline void hal_sio_v150_ct_set_set_tx_data_merge_en(sio_bus_t bus, uint32_t val)
481{
483 ct_set.d32 = sios_v150_regs(bus)->ct_set;
484 ct_set.b.tx_data_merge_en = val;
485 sios_v150_regs(bus)->ct_set = ct_set.d32;
486}
487
493static inline uint32_t hal_sio_v150_ct_set_get_rx_data_merge_en(sio_bus_t bus)
494{
496 ct_set.d32 = sios_v150_regs(bus)->ct_set;
497 return ct_set.b.rx_data_merge_en;
498}
499
505static inline void hal_sio_v150_ct_set_set_rx_data_merge_en(sio_bus_t bus, uint32_t val)
506{
508 ct_set.d32 = sios_v150_regs(bus)->ct_set;
509 ct_set.b.rx_data_merge_en = val;
510 sios_v150_regs(bus)->ct_set = ct_set.d32;
511}
512
518static inline uint32_t hal_sio_v150_ct_set_get_tx_fifo_disable(sio_bus_t bus)
519{
521 ct_set.d32 = sios_v150_regs(bus)->ct_set;
522 return ct_set.b.tx_fifo_disable;
523}
524
530static inline void hal_sio_v150_ct_set_set_tx_fifo_disable(sio_bus_t bus, uint32_t val)
531{
533 ct_set.d32 = sios_v150_regs(bus)->ct_set;
534 ct_set.b.tx_fifo_disable = val;
535 sios_v150_regs(bus)->ct_set = ct_set.d32;
536}
537
543static inline uint32_t hal_sio_v150_ct_set_get_rx_fifo_disable(sio_bus_t bus)
544{
546 ct_set.d32 = sios_v150_regs(bus)->ct_set;
547 return ct_set.b.rx_fifo_disable;
548}
549
555static inline void hal_sio_v150_ct_set_set_rx_fifo_disable(sio_bus_t bus, uint32_t val)
556{
558 ct_set.d32 = sios_v150_regs(bus)->ct_set;
559 ct_set.b.rx_fifo_disable = val;
560 sios_v150_regs(bus)->ct_set = ct_set.d32;
561}
562
568static inline uint32_t hal_sio_v150_ct_set_get_tx_enable(sio_bus_t bus)
569{
571 ct_set.d32 = sios_v150_regs(bus)->ct_set;
572 return ct_set.b.tx_enable;
573}
574
580static inline uint32_t hal_sio_v150_ct_set_get_rx_enable(sio_bus_t bus)
581{
583 ct_set.d32 = sios_v150_regs(bus)->ct_set;
584 return ct_set.b.rx_enable;
585}
586
592static inline uint32_t hal_sio_v150_ct_set_get_intr_en(sio_bus_t bus)
593{
595 ct_set.d32 = sios_v150_regs(bus)->ct_set;
596 return ct_set.b.intr_en;
597}
598
604static inline void hal_sio_v150_ct_set_set_intr_en(sio_bus_t bus, uint32_t val)
605{
607 ct_set.d32 = sios_v150_regs(bus)->ct_set;
608 ct_set.b.intr_en = val;
609 sios_v150_regs(bus)->ct_set = ct_set.d32;
610}
611
617static inline uint32_t hal_sio_v150_ct_set_get_rst_n(sio_bus_t bus)
618{
620 ct_set.d32 = sios_v150_regs(bus)->ct_set;
621 return ct_set.b.rst_n;
622}
623
629static inline void hal_sio_v150_ct_set_set_rst_n(sio_bus_t bus, uint32_t val)
630{
632 ct_set.d32 = sios_v150_regs(bus)->ct_set;
633 ct_set.b.rst_n = val;
634 sios_v150_regs(bus)->ct_set = ct_set.d32;
635}
636
642static inline uint32_t hal_sio_v150_rx_sta_get_rx_right_depth(sio_bus_t bus)
643{
645 rx_sta.d32 = sios_v150_regs(bus)->rx_sta;
646 return rx_sta.b.rx_right_depth;
647}
648
654static inline uint32_t hal_sio_v150_rx_sta_get_rx_left_depth(sio_bus_t bus)
655{
657 rx_sta.d32 = sios_v150_regs(bus)->rx_sta;
658 return rx_sta.b.rx_left_depth;
659}
660
666static inline uint32_t hal_sio_v150_tx_sta_get_tx_right_depth(sio_bus_t bus)
667{
669 tx_sta.d32 = sios_v150_regs(bus)->tx_sta;
670 return tx_sta.b.tx_right_depth;
671}
672
678static inline uint32_t hal_sio_v150_tx_sta_get_tx_left_depth(sio_bus_t bus)
679{
681 tx_sta.d32 = sios_v150_regs(bus)->tx_sta;
682 return tx_sta.b.tx_left_depth;
683}
684
690static inline uint32_t hal_sio_v150_data_width_set_get_tx(sio_bus_t bus)
691{
692 sio_v150_data_width_set_data_t data_width_set;
693 data_width_set.d32 = sios_v150_regs(bus)->data_width_set;
694 return data_width_set.b.tx;
695}
696
702static inline void hal_sio_v150_data_width_set_set_tx(sio_bus_t bus, uint32_t val)
703{
704 sio_v150_data_width_set_data_t data_width_set;
705 data_width_set.d32 = sios_v150_regs(bus)->data_width_set;
706 data_width_set.b.tx = val;
707 sios_v150_regs(bus)->data_width_set = data_width_set.d32;
708}
709
715static inline uint32_t hal_sio_v150_data_width_set_get_rx(sio_bus_t bus)
716{
717 sio_v150_data_width_set_data_t data_width_set;
718 data_width_set.d32 = sios_v150_regs(bus)->data_width_set;
719 return data_width_set.b.rx;
720}
721
727static inline void hal_sio_v150_data_width_set_set_rx(sio_bus_t bus, uint32_t val)
728{
729 sio_v150_data_width_set_data_t data_width_set;
730 data_width_set.d32 = sios_v150_regs(bus)->data_width_set;
731 data_width_set.b.rx = val;
732 sios_v150_regs(bus)->data_width_set = data_width_set.d32;
733}
734
740static inline uint32_t hal_sio_v150_start_pos_get_start_pos_write(sio_bus_t bus)
741{
742 sio_v150_i2s_start_pos_data_t i2s_start_pos;
743 i2s_start_pos.d32 = sios_v150_regs(bus)->i2s_start_pos;
744 return i2s_start_pos.b.start_pos_write;
745}
746
752static inline void hal_sio_v150_start_pos_set_start_pos_write(sio_bus_t bus, uint32_t val)
753{
754 sio_v150_i2s_start_pos_data_t i2s_start_pos;
755 i2s_start_pos.d32 = sios_v150_regs(bus)->i2s_start_pos;
756 i2s_start_pos.b.start_pos_write = val;
757 sios_v150_regs(bus)->i2s_start_pos = i2s_start_pos.d32;
758}
759
765static inline uint32_t hal_sio_v150_start_pos_get_start_pos_read(sio_bus_t bus)
766{
767 sio_v150_i2s_start_pos_data_t i2s_start_pos;
768 i2s_start_pos.d32 = sios_v150_regs(bus)->i2s_start_pos;
769 return i2s_start_pos.b.start_pos_read;
770}
771
777static inline void hal_sio_v150_start_pos_set_start_pos_read(sio_bus_t bus, uint32_t val)
778{
779 sio_v150_i2s_start_pos_data_t i2s_start_pos;
780 i2s_start_pos.d32 = sios_v150_regs(bus)->i2s_start_pos;
781 i2s_start_pos.b.start_pos_read = val;
782 sios_v150_regs(bus)->i2s_start_pos = i2s_start_pos.d32;
783}
784
790static inline uint32_t hal_sio_v150_pos_flag_get_start_pos_write(sio_bus_t bus)
791{
792 sio_v150_i2s_pos_flag_data_t i2s_pos_flag;
793 i2s_pos_flag.d32 = sios_v150_regs(bus)->i2s_pos_flag;
794 return i2s_pos_flag.b.start_pos_write;
795}
796
802static inline void hal_sio_v150_pos_flag_set_start_pos_write(sio_bus_t bus, uint32_t val)
803{
804 sio_v150_i2s_pos_flag_data_t i2s_pos_flag;
805 i2s_pos_flag.d32 = sios_v150_regs(bus)->i2s_pos_flag;
806 i2s_pos_flag.b.start_pos_write = val;
807 sios_v150_regs(bus)->i2s_pos_flag = i2s_pos_flag.d32;
808}
809
815static inline uint32_t hal_sio_v150_pos_flag_get_start_pos_read(sio_bus_t bus)
816{
817 sio_v150_i2s_pos_flag_data_t i2s_pos_flag;
818 i2s_pos_flag.d32 = sios_v150_regs(bus)->i2s_pos_flag;
819 return i2s_pos_flag.b.start_pos_read;
820}
821
827static inline void hal_sio_v150_pos_flag_set_start_pos_read(sio_bus_t bus, uint32_t val)
828{
829 sio_v150_i2s_pos_flag_data_t i2s_pos_flag;
830 i2s_pos_flag.d32 = sios_v150_regs(bus)->i2s_pos_flag;
831 i2s_pos_flag.b.start_pos_read = val;
832 sios_v150_regs(bus)->i2s_pos_flag = i2s_pos_flag.d32;
833}
834
840static inline uint32_t hal_sio_v150_ct_clr_get_tx_fifo_disable(sio_bus_t bus)
841{
843 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
844 return ct_clr.b.tx_fifo_disable;
845}
846
852static inline void hal_sio_v150_ct_clr_set_tx_fifo_disable(sio_bus_t bus, uint32_t val)
853{
855 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
856 ct_clr.b.tx_fifo_disable = val;
857 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
858}
859
865static inline uint32_t hal_sio_v150_ct_clr_get_rx_fifo_disable(sio_bus_t bus)
866{
868 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
869 return ct_clr.b.rx_fifo_disable;
870}
871
877static inline void hal_sio_v150_ct_clr_set_rx_fifo_disable(sio_bus_t bus, uint32_t val)
878{
880 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
881 ct_clr.b.rx_fifo_disable = val;
882 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
883}
884
890static inline uint32_t hal_sio_v150_ct_clr_get_tx_enable(sio_bus_t bus)
891{
893 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
894 return ct_clr.b.tx_enable;
895}
896
902static inline void hal_sio_v150_ct_clr_set_tx_enable(sio_bus_t bus, uint32_t val)
903{
905 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
906 ct_clr.b.tx_enable = val;
907 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
908}
909
915static inline uint32_t hal_sio_v150_ct_clr_get_rx_enable(sio_bus_t bus)
916{
918 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
919 return ct_clr.b.rx_enable;
920}
921
927static inline void hal_sio_v150_ct_clr_set_rx_enable(sio_bus_t bus, uint32_t val)
928{
930 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
931 ct_clr.b.rx_enable = val;
932 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
933}
934
940static inline void hal_sio_v150_ct_clr_set_intr_en(sio_bus_t bus, uint32_t val)
941{
943 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
944 ct_clr.b.intr_en = val;
945 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
946}
947
953static inline uint32_t hal_sio_v150_ct_clr_get_intr_en(sio_bus_t bus)
954{
956 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
957 return ct_clr.b.intr_en;
958}
959
965static inline void hal_sio_v150_ct_clr_set_rst_n(sio_bus_t bus, uint32_t val)
966{
968 ct_clr.d32 = sios_v150_regs(bus)->ct_clr;
969 ct_clr.b.rst_n = val;
970 sios_v150_regs(bus)->ct_clr = ct_clr.d32;
971}
972
977#ifdef __cplusplus
978#if __cplusplus
979}
980#endif /* __cplusplus */
981#endif /* __cplusplus */
982
983#endif
sio_bus_t
SIO(I2S/PCM) Bus.
Definition platform_core.h:254
#define I2S_MAX_NUMBER
Definition platform_core.h:138
void hal_sio_v150_regs_deinit(sio_bus_t bus)
Deinit the hal_sio which will clear the base address of registers has been set by hal_sio_v150_regs_i...
void hal_sio_v150_ct_set_set_tx_enable(sio_bus_t bus, uint32_t val)
Set the value of sio_v150_ct_set_data::tx_enable.
Definition hal_sio_v150_regs_op.c:15
uintptr_t g_hal_sio_regs[I2S_MAX_NUMBER]
Definition hal_sio.c:12
#define sios_v150_regs(bus)
Definition hal_sio_v150_regs_op.h:29
void hal_sio_v150_regs_init(sio_bus_t bus)
Init the sio which will set the base address of registers.
void hal_sio_v150_ct_set_set_rx_enable(sio_bus_t bus, uint32_t val)
Set the value of sio_v150_ct_set_data::rx_enable.
Definition hal_sio_v150_regs_op.c:31
unsigned int uintptr_t
Definition td_type.h:65
This union represents the bit fields in the sio_ct_clr register. Read the register into the d32 membe...
Definition hal_sio_v150_regs_def.h:197
uint32_t tx_enable
Definition hal_sio_v150_regs_def.h:214
uint32_t rx_enable
Definition hal_sio_v150_regs_def.h:217
uint32_t rst_n
Definition hal_sio_v150_regs_def.h:223
struct sio_v150_ct_clr_data::@274 b
uint32_t tx_fifo_disable
Definition hal_sio_v150_regs_def.h:208
uint32_t rx_fifo_disable
Definition hal_sio_v150_regs_def.h:211
uint32_t d32
Definition hal_sio_v150_regs_def.h:198
uint32_t intr_en
Definition hal_sio_v150_regs_def.h:220
This union represents the bit fields in the sio_ct_set register. Read the register into the d32 membe...
Definition hal_sio_v150_regs_def.h:161
uint32_t tx_fifo_threshold
Definition hal_sio_v150_regs_def.h:164
uint32_t tx_enable
Definition hal_sio_v150_regs_def.h:178
uint32_t tx_data_merge_en
Definition hal_sio_v150_regs_def.h:166
uint32_t d32
Definition hal_sio_v150_regs_def.h:162
uint32_t rx_fifo_threshold
Definition hal_sio_v150_regs_def.h:165
uint32_t rx_fifo_disable
Definition hal_sio_v150_regs_def.h:175
uint32_t tx_fifo_disable
Definition hal_sio_v150_regs_def.h:172
uint32_t rst_n
Definition hal_sio_v150_regs_def.h:187
struct sio_v150_ct_set_data::@273 b
uint32_t intr_en
Definition hal_sio_v150_regs_def.h:184
uint32_t rx_data_merge_en
Definition hal_sio_v150_regs_def.h:169
uint32_t rx_enable
Definition hal_sio_v150_regs_def.h:181
This union represents the bit fields in the sio_data_width_set register. Read the register into the d...
Definition hal_sio_v150_regs_def.h:261
uint32_t d32
Definition hal_sio_v150_regs_def.h:262
uint32_t tx
Definition hal_sio_v150_regs_def.h:264
struct sio_v150_data_width_set_data::@277 b
uint32_t rx
Definition hal_sio_v150_regs_def.h:265
This union represents the bit fields in the sio_pos_flag register. Read the register into the d32 mem...
Definition hal_sio_v150_regs_def.h:293
struct sio_v150_i2s_pos_flag_data::@279 b
uint32_t start_pos_read
Definition hal_sio_v150_regs_def.h:296
uint32_t d32
Definition hal_sio_v150_regs_def.h:294
uint32_t start_pos_write
Definition hal_sio_v150_regs_def.h:299
This union represents the bit fields in the sio_i2s_pos_merge_en register. Read the register into the...
Definition hal_sio_v150_regs_def.h:324
struct sio_v150_i2s_pos_merge_en_data::@281 b
uint32_t merge_en
Definition hal_sio_v150_regs_def.h:327
uint32_t d32
Definition hal_sio_v150_regs_def.h:325
This union represents the bit fields in the sio_i2s_start_pos register. Read the register into the d3...
Definition hal_sio_v150_regs_def.h:275
uint32_t start_pos_write
Definition hal_sio_v150_regs_def.h:281
uint32_t d32
Definition hal_sio_v150_regs_def.h:276
uint32_t start_pos_read
Definition hal_sio_v150_regs_def.h:278
struct sio_v150_i2s_start_pos_data::@278 b
This union represents the bit fields in the sio_intclr register. Read the register into the d32 membe...
Definition hal_sio_v150_regs_def.h:95
uint32_t rx_right_fifo_over
Definition hal_sio_v150_regs_def.h:100
struct sio_v150_intclr_data::@268 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:96
uint32_t rx_left_fifo_over
Definition hal_sio_v150_regs_def.h:101
uint32_t tx_right_fifo_under
Definition hal_sio_v150_regs_def.h:102
uint32_t tx_left_fifo_under
Definition hal_sio_v150_regs_def.h:103
uint32_t rx_intr
Definition hal_sio_v150_regs_def.h:98
uint32_t tx_intr
Definition hal_sio_v150_regs_def.h:99
This union represents the bit fields in the sio_intstatus register. Read the register into the d32 me...
Definition hal_sio_v150_regs_def.h:77
uint32_t tx_right_fifo_under
Definition hal_sio_v150_regs_def.h:84
uint32_t tx_intr
Definition hal_sio_v150_regs_def.h:81
uint32_t tx_left_fifo_under
Definition hal_sio_v150_regs_def.h:85
uint32_t rx_intr
Definition hal_sio_v150_regs_def.h:80
uint32_t rx_left_fifo_over
Definition hal_sio_v150_regs_def.h:83
uint32_t rx_right_fifo_over
Definition hal_sio_v150_regs_def.h:82
struct sio_v150_intstatus_data::@267 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:78
This union represents the bit fields in the left_rx_data register. Read the register into the d32 mem...
Definition hal_sio_v150_regs_def.h:137
struct sio_v150_left_rx_data::@271 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:138
uint32_t data
Definition hal_sio_v150_regs_def.h:140
This union represents the bit fields in the left_tx_data register. Read the register into the d32 mem...
Definition hal_sio_v150_regs_def.h:113
uint32_t data
Definition hal_sio_v150_regs_def.h:116
struct sio_v150_left_tx_data::@269 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:114
This union represents the bit fields in the sio_mode register. Read the register into the d32 member ...
Definition hal_sio_v150_regs_def.h:47
uint32_t d32
Definition hal_sio_v150_regs_def.h:48
uint32_t clk_edge
Definition hal_sio_v150_regs_def.h:65
uint32_t chn_num
Definition hal_sio_v150_regs_def.h:60
uint32_t mode
Definition hal_sio_v150_regs_def.h:50
uint32_t ext_rec_en
Definition hal_sio_v150_regs_def.h:57
uint32_t pcm_mode
Definition hal_sio_v150_regs_def.h:53
struct sio_v150_mode_data::@266 b
This union represents the bit fields in the right_rx_data register. Read the register into the d32 me...
Definition hal_sio_v150_regs_def.h:149
uint32_t data
Definition hal_sio_v150_regs_def.h:152
struct sio_v150_right_rx_data::@272 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:150
This union represents the bit fields in the right_tx_data register. Read the register into the d32 me...
Definition hal_sio_v150_regs_def.h:125
uint32_t d32
Definition hal_sio_v150_regs_def.h:126
struct sio_v150_right_tx_data::@270 b
uint32_t data
Definition hal_sio_v150_regs_def.h:128
This union represents the bit fields in the sio_rx_sta register. Read the register into the d32 membe...
Definition hal_sio_v150_regs_def.h:233
uint32_t rx_right_depth
Definition hal_sio_v150_regs_def.h:236
struct sio_v150_rx_sta_data::@275 b
uint32_t d32
Definition hal_sio_v150_regs_def.h:234
uint32_t rx_left_depth
Definition hal_sio_v150_regs_def.h:237
This union represents the bit fields in the sio_tx_sta register. Read the register into the d32 membe...
Definition hal_sio_v150_regs_def.h:247
uint32_t tx_left_depth
Definition hal_sio_v150_regs_def.h:251
struct sio_v150_tx_sta_data::@276 b
uint32_t tx_right_depth
Definition hal_sio_v150_regs_def.h:250
uint32_t d32
Definition hal_sio_v150_regs_def.h:248
This union represents the bit fields in the sio_version register. Read the register into the d32 memb...
Definition hal_sio_v150_regs_def.h:31
uint32_t d32
Definition hal_sio_v150_regs_def.h:32
struct sio_v150_version_data::@265 b
uint32_t loop
Definition hal_sio_v150_regs_def.h:35