fe_hal_rf_reg_if.h 文件参考

#include "osal_types.h"

fe_hal_rf_reg_if.h 的引用(Include)关系图:

此图展示该文件直接或间接的被哪些文件引用了:

浏览源代码.

宏定义
#define	OFFSET_WB_LOCAL_CTRL_EN_REG0   0
#define	OFFSET_WB_LOCAL_CTRL_EN_REG1   1
#define	OFFSET_WB_LOCAL_CTRL_TX_REG2   2
#define	OFFSET_WB_LOCAL_CTRL_TX_REG3   3
#define	OFFSET_WB_LOCAL_CTRL_GAIN_REG4   4
#define	OFFSET_WB_LOCAL_CTRL_GAIN_REG5   5
#define	OFFSET_WB_LOCAL_CTRL_DCOC_REG6   6
#define	OFFSET_WB_MODE_SEL_0_REG7   7
#define	OFFSET_WB_MODE_SEL_1_REG8   8
#define	OFFSET_WB_RF_LO_TX_ENABLE_REG9   9
#define	OFFSET_WB_RF_RX_ENABLE_REG10   10
#define	OFFSET_WB_RF_ABB_ENABLE_REG11   11
#define	OFFSET_WB_RF_LO_TX_TOP_TEST_REG12   12
#define	OFFSET_WB_RF_RX_TOP_TEST_REG13   13
#define	OFFSET_WB_RF_ABB_TEST_REG14   14
#define	OFFSET_WB_ADC_CTRL0_REG15   15
#define	OFFSET_WB_ADC_CTRL1_REG16   16
#define	OFFSET_WB_DAC_CTRL0_REG17   17
#define	OFFSET_WB_DAC_CTRL1_REG18   18
#define	OFFSET_WB_TEST_MUX_SWITCH_REG19   19
#define	OFFSET_WL_RF_TRX_RC_CODE1_REG20   20
#define	OFFSET_WL_RF_TRX_RC_CODE1_REG21   21
#define	OFFSET_BT_RF_TRX_RC_CODE1_REG22   22
#define	OFFSET_BT_RF_TRX_RC_CODE1_REG23   23
#define	OFFSET_WB_RF_TX_RC_CODE2_REG24   24
#define	OFFSET_WB_RF_TRX_IQCAL_CONTROL_REG25   25
#define	OFFSET_WB_RF_TRX_SWAP_REG26   26
#define	OFFSET_WB_RFABB_LPF_BW_MAP_REG27   27
#define	OFFSET_WB_FB_EN_LUT1_REG28   28
#define	OFFSET_WB_FB_EN_LUT1_REG29   29
#define	OFFSET_WB_FB_EN_LUT1_REG30   30
#define	OFFSET_WB_FB_EN_LUT1_REG31   31
#define	OFFSET_WB_FB_EN_LUT1_REG32   32
#define	OFFSET_WB_FB_EN_LUT1_REG33   33
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG34   34
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG35   35
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG36   36
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG37   37
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG38   38
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG39   39
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG40   40
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG41   41
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG42   42
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG43   43
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG44   44
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG45   45
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG46   46
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG47   47
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG48   48
#define	OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG49   49
#define	OFFSET_WB_RF_LOGEN_2G_TRIM_REG50   50
#define	OFFSET_D_WB_RF_LOGEN_SSB_TUNE_REG51   51
#define	OFFSET_D_WB_RF_LOGEN_SSB_IFB_GAIN_TRIM_REG52   52
#define	OFFSET_WB_RF_RX_SETUP_REG53   53
#define	OFFSET_WB_RF_RX_MANUAL1_REG54   54
#define	OFFSET_WB_RF_RX_MANUAL1_REG55   55
#define	OFFSET_WB_RF_RX_MANUAL2_REG56   56
#define	OFFSET_WB_RF_RX_MANUAL3_REG57   57
#define	OFFSET_WB_RF_RX_LNA_MUX1_REG58   58
#define	OFFSET_WB_RF_RX_LNA_MUX2_REG59   59
#define	OFFSET_WB_RF_RX_LNA_MUX3_REG60   60
#define	OFFSET_WB_RF_RX_LNA_MUX4_REG61   61
#define	OFFSET_WB_RF_RX_LNA_MUX5_REG62   62
#define	OFFSET_WB_RF_RX_LNA_MUX6_REG63   63
#define	OFFSET_WB_RF_RX_LNA_MUX7_REG64   64
#define	OFFSET_WB_RF_RX_LNA_MUX8_REG65   65
#define	OFFSET_WB_RF_RX_LNA_MUX9_REG66   66
#define	OFFSET_WB_RF_RX_LNA_MUX10_REG67   67
#define	OFFSET_WB_RF_RX_LNA_MUX3_REG68   68
#define	OFFSET_WB_RF_RX_LNA_MUX5_REG69   69
#define	OFFSET_WB_RF_RX_LNA_MUX5_REG70   70
#define	OFFSET_WB_RF_RX_LNA_MUX11_REG71   71
#define	OFFSET_WB_RF_RX_LNA_MUX12_REG72   72
#define	OFFSET_WB_RF_RX_LNA_MUX13_REG73   73
#define	OFFSET_WB_RF_RX_LNA_MUX14_REG74   74
#define	OFFSET_WB_RF_RX_LNA_MUX15_REG75   75
#define	OFFSET_WB_RF_RX_LNA_MUX16_REG76   76
#define	OFFSET_WB_RF_RX_LNA_MUX17_REG77   77
#define	OFFSET_WB_RF_RX_LNA_MUX18_REG78   78
#define	OFFSET_WB_RF_RX_LNA_MUX15_REG79   79
#define	OFFSET_WB_RF_RX_LNA_MUX16_REG80   80
#define	OFFSET_WB_RF_RX_LNA_MUX17_REG81   81
#define	OFFSET_WB_RF_RX_LNA_MUX18_REG82   82
#define	OFFSET_WB_RF_RX_LNA_BIAS_CONTROL1_REG83   83
#define	OFFSET_WB_RF_RX_LNA_BIAS_CONTROL2_REG84   84
#define	OFFSET_WB_RF_RX_MIX_TIA_MUX1_REG85   85
#define	OFFSET_WB_RF_RX_MIX_TIA_MUX2_REG86   86
#define	OFFSET_WB_RF_RX_MIX_TIA_MUX3_REG87   87
#define	OFFSET_WB_RF_RX_MIX_TIA_MUX4_REG88   88
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG89   89
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG90   90
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG91   91
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG92   92
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG93   93
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG94   94
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG95   95
#define	OFFSET_WB_RF_RX_GAIN_LUT_REG96   96
#define	OFFSET_WB_TX_RF_CONFIG_REG97   97
#define	OFFSET_WB_TX_RF_CALIBRATION_REG98   98
#define	OFFSET_WB_TX_TRIM_BIAS_MODE_REG99   99
#define	OFFSET_WB_TX_PA_TRIM_MANUAL_REG100   100
#define	OFFSET_WB_TX_PA_TRIM_MANUAL_REG101   101
#define	OFFSET_WB_TX_PA_TRIM_MANUAL_REG102   102
#define	OFFSET_WB_TX_TRIM_BIAS_MANUAL_REG103   103
#define	OFFSET_TIA_VCM_REG104   104
#define	OFFSET_TIA_IBG_REG105   105
#define	OFFSET_TIA_CC_REG106   106
#define	OFFSET_TIA_CMFB_R_REG107   107
#define	OFFSET_LPF_VCM_REG108   108
#define	OFFSET_LPF_VCM_REG109   109
#define	OFFSET_LPF_IBG_REG110   110
#define	OFFSET_LPF_IBG_REG111   111
#define	OFFSET_LPF_RIPCAL_REG112   112
#define	OFFSET_LPF_RIPCAL_REG113   113
#define	OFFSET_LPF_RIPCAL_REG114   114
#define	OFFSET_LPF_CC_REG115   115
#define	OFFSET_LPF_RZ_REG116   116
#define	OFFSET_LPF_CMFB_R_REG117   117
#define	OFFSET_LPF_ITRIM_REG118   118
#define	OFFSET_VGA_VCM_REG119   119
#define	OFFSET_VGA_IBG_REG120   120
#define	OFFSET_VGA_ITRIM_REG121   121
#define	OFFSET_VGA_CC_LUT_REG122   122
#define	OFFSET_VGA_CC_LUT2_REG123   123
#define	OFFSET_VGA_RZ_LUT1_REG124   124
#define	OFFSET_VGA_CMFB_R_LUT1_REG125   125
#define	OFFSET_VGA_CMFB_R_LUT5_REG126   126
#define	OFFSET_DCOC_REG127   127
#define	OFFSET_WL_TX_PDET2G_CTRL_REG128   128
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG129   129
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG130   130
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG131   131
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG132   132
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG133   133
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG134   134
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG135   135
#define	OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG136   136
#define	OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG137   137
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG138   138
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG139   139
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG140   140
#define	OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG141   141
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG142   142
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG143   143
#define	OFFSET_WB_RF_TX_PA_VB_LUT_REG144   144
#define	OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG145   145
#define	OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG146   146
#define	OFFSET_RESERVED_REG_REG147   147
#define	OFFSET_WL_TX_PDET2G_CTRL_REG148   148
#define	CALI_RF_RC_CODE_BITS   6
#define	CALI_RF_CAP_BANK_BW_I_OFST   BIT_OFFSET_0
#define	CALI_RF_CAP_BANK_BW_Q_OFST   BIT_OFFSET_8
#define	CALI_RF_RC_END_OFST   BIT_OFFSET_15
#define	CALI_RF_RC_TUNE_END_BITS   1
#define	CALI_RF_2G_UPC_PPA_BITS   5
#define	CALI_RF_RC_TUNE_COMP   1
#define	CALI_RF_RC_TUNE_INIT   0
#define	CALI_RF_PA_2G_CSW_MAX_VAL   32
#define	CALI_RF_PA_2G_LCTUNE_MAX_VAL   32
#define	CALI_RF_TX_IQ_LVL_USED_NUM   2
#define	CALI_RF_RX_IQ_LVL_USED_NUM   2
#define	CALI_RF_TX_DC_LVL_USED_NUM   2
#define	CALI_RF_IQ_PHASE_MIN_VALUE   350
#define	CALI_RF_IQ_PHASE_THR_VALUE   (1 << 0x9)
#define	CALI_RF_IQ_PHASE_RECT_VALUE   (1 << 0xA)
#define	CALI_IQ_PHASE_SHIFT_TONE_FREQ   2500
#define	CALI_RF_RX_DC_FIX_BIT   (8) /* rx dc vga 最小增益值 定点化放大位数 */
#define	CALI_RF_RX_DC_DEFAULT_ANALOG_COMP   (0x8080) /* rx dc 默认的模拟补偿值 */
#define	CALI_RF_RX_DC_VGA_LVL_USED_NUM   (2) /* rx dc补偿值vga档位数目 */
#define	CALI_RF_RX_DC_VGA_MAX_GAIN   (2560) /* rx dc vga 最大增益值 定点化放大 */
#define	CALI_RF_RX_DC_VGA_MIN_GAIN   (322) /* rx dc vga 最小增益值 定点化放大 */
#define	CALI_RF_TX_DC_DC3_VALUE   0x100 /* DC3=(64mv/512mv)*2048=256 */
#define	CALI_20M_BANDWIDTH_ADJUST   129 /* ACI刷新20M的RC CODE缩放值 */
#define	HH503_RF_FREQ_2_CHANNEL_NUM   14 /* 2g支持信道数目 */
#define	HH503_RF_FREQ_5_CHANNEL_NUM   29 /* 5g支持信道数目 */
#define	CALI_RF_ADDR_SHIFT_BITS   2
#define	HH503_WL_PLL1_RFLDO789_ENABLE   0xFF00
#define	HAL_2G_TX_PWR_VAL_MAX   (0x1F3F) /* ppa code限定最大值 */
#define	HAL_2G_TX_PWR_VAL_MIN   (0x1101) /* ppa code限定最小值 */
#define	HAL_2G_TX_PWR_VAL_DEFAULT   (0x1C32) /* ppa code超过限定值时的赋值 */
#define	HAL_TXPWR_SEARCH_UPC_MAX   (0x1F3F)
#define	HAL_TXPWR_SEARCH_UPC_MIN   (0x1101)
#define	HAL_TXPWR_SEARCH_UPC_NORMAL   (0x1C32)
#define	HAL_TXPWR_SEARCH_UPC_TH   (0x1F)
#define	HAL_TXPWR_SEARCH_UPC_STEP   (0x05)

类型定义
typedef osal_u8	fe_hal_rf_reg_type_enum_uint8
typedef osal_u8	fe_hal_rf_2g_band_sel_enum_uint8
typedef osal_u8	fe_hal_rf_ctune_val_index_enum_uint8

枚举
enum	fe_hal_rf_reg_type_enum { RF_REG = 0 , PLL_REG = 1 , SOC_REG = 2 , REG_BUTT }
enum	fe_hal_rf_2g_band_sel_enum { CALI_RF_2G_BAND_SEL_1 = 1 , CALI_RF_2G_BAND_SEL_2 , CALI_RF_2G_BAND_SEL_3 , CALI_RF_2G_BAND_SEL_BUTT }
enum	fe_hal_rf_ctune_val_index_enum {   CALI_RF_CTUNE_VAL_INDEX_0 , CALI_RF_CTUNE_VAL_INDEX_1 , CALI_RF_CTUNE_VAL_INDEX_2 , CALI_RF_CTUNE_VAL_INDEX_3 ,   CALI_RF_CTUNE_VAL_INDEX_4 , CALI_RF_CTUNE_VAL_INDEX_5 , CALI_RF_CTUNE_VAL_INDEX_6 , CALI_RF_CTUNE_VAL_INDEX_7 ,   CALI_RF_CTUNE_VAL_INDEX_BUTT }

函数
osal_void	hal_rf_set_abb2_d_wb_ppa_code_unit_local (osal_u16 ppa_code_unit)
osal_void	hal_rf_set_abb2_d_wb_ppa_code_gm_local (osal_u16 ppa_code_gm)
osal_void	hal_soc_cfg_dac_index_man (osal_u16 dac_index)
osal_u32	hal_rf_get_soc_reg_base (osal_u8 rf_id)
osal_void	hal_rf_set_pll1_reg (osal_u16 pll_top)
osal_void	hal_rf_set_pll2_reg (osal_u16 div_int)
osal_u8	hal_rf_get_fb_gain_lna_lut (osal_u8 fb_gain_local)

宏定义说明

CALI_20M_BANDWIDTH_ADJUST

#define CALI_20M_BANDWIDTH_ADJUST   129 /* ACI刷新20M的RC CODE缩放值 */

CALI_IQ_PHASE_SHIFT_TONE_FREQ

#define CALI_IQ_PHASE_SHIFT_TONE_FREQ   2500

CALI_RF_2G_UPC_PPA_BITS

#define CALI_RF_2G_UPC_PPA_BITS   5

CALI_RF_ADDR_SHIFT_BITS

#define CALI_RF_ADDR_SHIFT_BITS   2

CALI_RF_CAP_BANK_BW_I_OFST

#define CALI_RF_CAP_BANK_BW_I_OFST   BIT_OFFSET_0

CALI_RF_CAP_BANK_BW_Q_OFST

#define CALI_RF_CAP_BANK_BW_Q_OFST   BIT_OFFSET_8

CALI_RF_IQ_PHASE_MIN_VALUE

#define CALI_RF_IQ_PHASE_MIN_VALUE   350

CALI_RF_IQ_PHASE_RECT_VALUE

#define CALI_RF_IQ_PHASE_RECT_VALUE   (1 << 0xA)

CALI_RF_IQ_PHASE_THR_VALUE

#define CALI_RF_IQ_PHASE_THR_VALUE   (1 << 0x9)

CALI_RF_PA_2G_CSW_MAX_VAL

#define CALI_RF_PA_2G_CSW_MAX_VAL   32

CALI_RF_PA_2G_LCTUNE_MAX_VAL

#define CALI_RF_PA_2G_LCTUNE_MAX_VAL   32

CALI_RF_RC_CODE_BITS

#define CALI_RF_RC_CODE_BITS   6

CALI_RF_RC_END_OFST

#define CALI_RF_RC_END_OFST   BIT_OFFSET_15

CALI_RF_RC_TUNE_COMP

#define CALI_RF_RC_TUNE_COMP   1

CALI_RF_RC_TUNE_END_BITS

#define CALI_RF_RC_TUNE_END_BITS   1

CALI_RF_RC_TUNE_INIT

#define CALI_RF_RC_TUNE_INIT   0

CALI_RF_RX_DC_DEFAULT_ANALOG_COMP

#define CALI_RF_RX_DC_DEFAULT_ANALOG_COMP   (0x8080) /* rx dc 默认的模拟补偿值 */

CALI_RF_RX_DC_FIX_BIT

#define CALI_RF_RX_DC_FIX_BIT   (8) /* rx dc vga 最小增益值 定点化放大位数 */

CALI_RF_RX_DC_VGA_LVL_USED_NUM

#define CALI_RF_RX_DC_VGA_LVL_USED_NUM   (2) /* rx dc补偿值vga档位数目 */

CALI_RF_RX_DC_VGA_MAX_GAIN

#define CALI_RF_RX_DC_VGA_MAX_GAIN   (2560) /* rx dc vga 最大增益值 定点化放大 */

CALI_RF_RX_DC_VGA_MIN_GAIN

#define CALI_RF_RX_DC_VGA_MIN_GAIN   (322) /* rx dc vga 最小增益值 定点化放大 */

CALI_RF_RX_IQ_LVL_USED_NUM

#define CALI_RF_RX_IQ_LVL_USED_NUM   2

CALI_RF_TX_DC_DC3_VALUE

#define CALI_RF_TX_DC_DC3_VALUE   0x100 /* DC3=(64mv/512mv)*2048=256 */

CALI_RF_TX_DC_LVL_USED_NUM

#define CALI_RF_TX_DC_LVL_USED_NUM   2

CALI_RF_TX_IQ_LVL_USED_NUM

#define CALI_RF_TX_IQ_LVL_USED_NUM   2

HAL_2G_TX_PWR_VAL_DEFAULT

#define HAL_2G_TX_PWR_VAL_DEFAULT   (0x1C32) /* ppa code超过限定值时的赋值 */

HAL_2G_TX_PWR_VAL_MAX

#define HAL_2G_TX_PWR_VAL_MAX   (0x1F3F) /* ppa code限定最大值 */

HAL_2G_TX_PWR_VAL_MIN

#define HAL_2G_TX_PWR_VAL_MIN   (0x1101) /* ppa code限定最小值 */

HAL_TXPWR_SEARCH_UPC_MAX

#define HAL_TXPWR_SEARCH_UPC_MAX   (0x1F3F)

HAL_TXPWR_SEARCH_UPC_MIN

#define HAL_TXPWR_SEARCH_UPC_MIN   (0x1101)

HAL_TXPWR_SEARCH_UPC_NORMAL

#define HAL_TXPWR_SEARCH_UPC_NORMAL   (0x1C32)

HAL_TXPWR_SEARCH_UPC_STEP

#define HAL_TXPWR_SEARCH_UPC_STEP   (0x05)

HAL_TXPWR_SEARCH_UPC_TH

#define HAL_TXPWR_SEARCH_UPC_TH   (0x1F)

HH503_RF_FREQ_2_CHANNEL_NUM

#define HH503_RF_FREQ_2_CHANNEL_NUM   14 /* 2g支持信道数目 */

HH503_RF_FREQ_5_CHANNEL_NUM

#define HH503_RF_FREQ_5_CHANNEL_NUM   29 /* 5g支持信道数目 */

HH503_WL_PLL1_RFLDO789_ENABLE

#define HH503_WL_PLL1_RFLDO789_ENABLE   0xFF00

OFFSET_BT_RF_TRX_RC_CODE1_REG22

#define OFFSET_BT_RF_TRX_RC_CODE1_REG22   22

OFFSET_BT_RF_TRX_RC_CODE1_REG23

#define OFFSET_BT_RF_TRX_RC_CODE1_REG23   23

OFFSET_D_WB_RF_LOGEN_SSB_IFB_GAIN_TRIM_REG52

#define OFFSET_D_WB_RF_LOGEN_SSB_IFB_GAIN_TRIM_REG52   52

OFFSET_D_WB_RF_LOGEN_SSB_TUNE_REG51

#define OFFSET_D_WB_RF_LOGEN_SSB_TUNE_REG51   51

OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG137

#define OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG137   137

OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG146

#define OFFSET_D_WB_RF_TX_PA_VMID_LUT_REG146   146

OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG136

#define OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG136   136

OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG145

#define OFFSET_D_WB_RF_TX_PPA_VBC_SEL_LUT_REG145   145

OFFSET_DCOC_REG127

#define OFFSET_DCOC_REG127   127

OFFSET_LPF_CC_REG115

#define OFFSET_LPF_CC_REG115   115

OFFSET_LPF_CMFB_R_REG117

#define OFFSET_LPF_CMFB_R_REG117   117

OFFSET_LPF_IBG_REG110

#define OFFSET_LPF_IBG_REG110   110

OFFSET_LPF_IBG_REG111

#define OFFSET_LPF_IBG_REG111   111

OFFSET_LPF_ITRIM_REG118

#define OFFSET_LPF_ITRIM_REG118   118

OFFSET_LPF_RIPCAL_REG112

#define OFFSET_LPF_RIPCAL_REG112   112

OFFSET_LPF_RIPCAL_REG113

#define OFFSET_LPF_RIPCAL_REG113   113

OFFSET_LPF_RIPCAL_REG114

#define OFFSET_LPF_RIPCAL_REG114   114

OFFSET_LPF_RZ_REG116

#define OFFSET_LPF_RZ_REG116   116

OFFSET_LPF_VCM_REG108

#define OFFSET_LPF_VCM_REG108   108

OFFSET_LPF_VCM_REG109

#define OFFSET_LPF_VCM_REG109   109

OFFSET_RESERVED_REG_REG147

#define OFFSET_RESERVED_REG_REG147   147

OFFSET_TIA_CC_REG106

#define OFFSET_TIA_CC_REG106   106

OFFSET_TIA_CMFB_R_REG107

#define OFFSET_TIA_CMFB_R_REG107   107

OFFSET_TIA_IBG_REG105

#define OFFSET_TIA_IBG_REG105   105

OFFSET_TIA_VCM_REG104

#define OFFSET_TIA_VCM_REG104   104

OFFSET_VGA_CC_LUT2_REG123

#define OFFSET_VGA_CC_LUT2_REG123   123

OFFSET_VGA_CC_LUT_REG122

#define OFFSET_VGA_CC_LUT_REG122   122

OFFSET_VGA_CMFB_R_LUT1_REG125

#define OFFSET_VGA_CMFB_R_LUT1_REG125   125

OFFSET_VGA_CMFB_R_LUT5_REG126

#define OFFSET_VGA_CMFB_R_LUT5_REG126   126

OFFSET_VGA_IBG_REG120

#define OFFSET_VGA_IBG_REG120   120

OFFSET_VGA_ITRIM_REG121

#define OFFSET_VGA_ITRIM_REG121   121

OFFSET_VGA_RZ_LUT1_REG124

#define OFFSET_VGA_RZ_LUT1_REG124   124

OFFSET_VGA_VCM_REG119

#define OFFSET_VGA_VCM_REG119   119

OFFSET_WB_ADC_CTRL0_REG15

#define OFFSET_WB_ADC_CTRL0_REG15   15

OFFSET_WB_ADC_CTRL1_REG16

#define OFFSET_WB_ADC_CTRL1_REG16   16

OFFSET_WB_DAC_CTRL0_REG17

#define OFFSET_WB_DAC_CTRL0_REG17   17

OFFSET_WB_DAC_CTRL1_REG18

#define OFFSET_WB_DAC_CTRL1_REG18   18

OFFSET_WB_FB_EN_LUT1_REG28

#define OFFSET_WB_FB_EN_LUT1_REG28   28

OFFSET_WB_FB_EN_LUT1_REG29

#define OFFSET_WB_FB_EN_LUT1_REG29   29

OFFSET_WB_FB_EN_LUT1_REG30

#define OFFSET_WB_FB_EN_LUT1_REG30   30

OFFSET_WB_FB_EN_LUT1_REG31

#define OFFSET_WB_FB_EN_LUT1_REG31   31

OFFSET_WB_FB_EN_LUT1_REG32

#define OFFSET_WB_FB_EN_LUT1_REG32   32

OFFSET_WB_FB_EN_LUT1_REG33

#define OFFSET_WB_FB_EN_LUT1_REG33   33

OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG34

#define OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG34   34

OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG35

#define OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG35   35

OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG42

#define OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG42   42

OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG43

#define OFFSET_WB_FB_GAIN_LUT_CTRL_1_REG43   43

OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG36

#define OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG36   36

OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG44

#define OFFSET_WB_FB_GAIN_LUT_CTRL_2_REG44   44

OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG37

#define OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG37   37

OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG45

#define OFFSET_WB_FB_GAIN_LUT_CTRL_3_REG45   45

OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG38

#define OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG38   38

OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG46

#define OFFSET_WB_FB_GAIN_LUT_CTRL_4_REG46   46

OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG39

#define OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG39   39

OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG47

#define OFFSET_WB_FB_GAIN_LUT_CTRL_5_REG47   47

OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG40

#define OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG40   40

OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG48

#define OFFSET_WB_FB_GAIN_LUT_CTRL_6_REG48   48

OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG41

#define OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG41   41

OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG49

#define OFFSET_WB_FB_GAIN_LUT_CTRL_7_REG49   49

OFFSET_WB_LOCAL_CTRL_DCOC_REG6

#define OFFSET_WB_LOCAL_CTRL_DCOC_REG6   6

OFFSET_WB_LOCAL_CTRL_EN_REG0

#define OFFSET_WB_LOCAL_CTRL_EN_REG0   0

OFFSET_WB_LOCAL_CTRL_EN_REG1

#define OFFSET_WB_LOCAL_CTRL_EN_REG1   1

OFFSET_WB_LOCAL_CTRL_GAIN_REG4

#define OFFSET_WB_LOCAL_CTRL_GAIN_REG4   4

OFFSET_WB_LOCAL_CTRL_GAIN_REG5

#define OFFSET_WB_LOCAL_CTRL_GAIN_REG5   5

OFFSET_WB_LOCAL_CTRL_TX_REG2

#define OFFSET_WB_LOCAL_CTRL_TX_REG2   2

OFFSET_WB_LOCAL_CTRL_TX_REG3

#define OFFSET_WB_LOCAL_CTRL_TX_REG3   3

OFFSET_WB_MODE_SEL_0_REG7

#define OFFSET_WB_MODE_SEL_0_REG7   7

OFFSET_WB_MODE_SEL_1_REG8

#define OFFSET_WB_MODE_SEL_1_REG8   8

OFFSET_WB_RF_ABB_ENABLE_REG11

#define OFFSET_WB_RF_ABB_ENABLE_REG11   11

OFFSET_WB_RF_ABB_TEST_REG14

#define OFFSET_WB_RF_ABB_TEST_REG14   14

OFFSET_WB_RF_LO_TX_ENABLE_REG9

#define OFFSET_WB_RF_LO_TX_ENABLE_REG9   9

OFFSET_WB_RF_LO_TX_TOP_TEST_REG12

#define OFFSET_WB_RF_LO_TX_TOP_TEST_REG12   12

OFFSET_WB_RF_LOGEN_2G_TRIM_REG50

#define OFFSET_WB_RF_LOGEN_2G_TRIM_REG50   50

OFFSET_WB_RF_RX_ENABLE_REG10

#define OFFSET_WB_RF_RX_ENABLE_REG10   10

OFFSET_WB_RF_RX_GAIN_LUT_REG89

#define OFFSET_WB_RF_RX_GAIN_LUT_REG89   89

OFFSET_WB_RF_RX_GAIN_LUT_REG90

#define OFFSET_WB_RF_RX_GAIN_LUT_REG90   90

OFFSET_WB_RF_RX_GAIN_LUT_REG91

#define OFFSET_WB_RF_RX_GAIN_LUT_REG91   91

OFFSET_WB_RF_RX_GAIN_LUT_REG92

#define OFFSET_WB_RF_RX_GAIN_LUT_REG92   92

OFFSET_WB_RF_RX_GAIN_LUT_REG93

#define OFFSET_WB_RF_RX_GAIN_LUT_REG93   93

OFFSET_WB_RF_RX_GAIN_LUT_REG94

#define OFFSET_WB_RF_RX_GAIN_LUT_REG94   94

OFFSET_WB_RF_RX_GAIN_LUT_REG95

#define OFFSET_WB_RF_RX_GAIN_LUT_REG95   95

OFFSET_WB_RF_RX_GAIN_LUT_REG96

#define OFFSET_WB_RF_RX_GAIN_LUT_REG96   96

OFFSET_WB_RF_RX_LNA_BIAS_CONTROL1_REG83

#define OFFSET_WB_RF_RX_LNA_BIAS_CONTROL1_REG83   83

OFFSET_WB_RF_RX_LNA_BIAS_CONTROL2_REG84

#define OFFSET_WB_RF_RX_LNA_BIAS_CONTROL2_REG84   84

OFFSET_WB_RF_RX_LNA_MUX10_REG67

#define OFFSET_WB_RF_RX_LNA_MUX10_REG67   67

OFFSET_WB_RF_RX_LNA_MUX11_REG71

#define OFFSET_WB_RF_RX_LNA_MUX11_REG71   71

OFFSET_WB_RF_RX_LNA_MUX12_REG72

#define OFFSET_WB_RF_RX_LNA_MUX12_REG72   72

OFFSET_WB_RF_RX_LNA_MUX13_REG73

#define OFFSET_WB_RF_RX_LNA_MUX13_REG73   73

OFFSET_WB_RF_RX_LNA_MUX14_REG74

#define OFFSET_WB_RF_RX_LNA_MUX14_REG74   74

OFFSET_WB_RF_RX_LNA_MUX15_REG75

#define OFFSET_WB_RF_RX_LNA_MUX15_REG75   75

OFFSET_WB_RF_RX_LNA_MUX15_REG79

#define OFFSET_WB_RF_RX_LNA_MUX15_REG79   79

OFFSET_WB_RF_RX_LNA_MUX16_REG76

#define OFFSET_WB_RF_RX_LNA_MUX16_REG76   76

OFFSET_WB_RF_RX_LNA_MUX16_REG80

#define OFFSET_WB_RF_RX_LNA_MUX16_REG80   80

OFFSET_WB_RF_RX_LNA_MUX17_REG77

#define OFFSET_WB_RF_RX_LNA_MUX17_REG77   77

OFFSET_WB_RF_RX_LNA_MUX17_REG81

#define OFFSET_WB_RF_RX_LNA_MUX17_REG81   81

OFFSET_WB_RF_RX_LNA_MUX18_REG78

#define OFFSET_WB_RF_RX_LNA_MUX18_REG78   78

OFFSET_WB_RF_RX_LNA_MUX18_REG82

#define OFFSET_WB_RF_RX_LNA_MUX18_REG82   82

OFFSET_WB_RF_RX_LNA_MUX1_REG58

#define OFFSET_WB_RF_RX_LNA_MUX1_REG58   58

OFFSET_WB_RF_RX_LNA_MUX2_REG59

#define OFFSET_WB_RF_RX_LNA_MUX2_REG59   59

OFFSET_WB_RF_RX_LNA_MUX3_REG60

#define OFFSET_WB_RF_RX_LNA_MUX3_REG60   60

OFFSET_WB_RF_RX_LNA_MUX3_REG68

#define OFFSET_WB_RF_RX_LNA_MUX3_REG68   68

OFFSET_WB_RF_RX_LNA_MUX4_REG61

#define OFFSET_WB_RF_RX_LNA_MUX4_REG61   61

OFFSET_WB_RF_RX_LNA_MUX5_REG62

#define OFFSET_WB_RF_RX_LNA_MUX5_REG62   62

OFFSET_WB_RF_RX_LNA_MUX5_REG69

#define OFFSET_WB_RF_RX_LNA_MUX5_REG69   69

OFFSET_WB_RF_RX_LNA_MUX5_REG70

#define OFFSET_WB_RF_RX_LNA_MUX5_REG70   70

OFFSET_WB_RF_RX_LNA_MUX6_REG63

#define OFFSET_WB_RF_RX_LNA_MUX6_REG63   63

OFFSET_WB_RF_RX_LNA_MUX7_REG64

#define OFFSET_WB_RF_RX_LNA_MUX7_REG64   64

OFFSET_WB_RF_RX_LNA_MUX8_REG65

#define OFFSET_WB_RF_RX_LNA_MUX8_REG65   65

OFFSET_WB_RF_RX_LNA_MUX9_REG66

#define OFFSET_WB_RF_RX_LNA_MUX9_REG66   66

OFFSET_WB_RF_RX_MANUAL1_REG54

#define OFFSET_WB_RF_RX_MANUAL1_REG54   54

OFFSET_WB_RF_RX_MANUAL1_REG55

#define OFFSET_WB_RF_RX_MANUAL1_REG55   55

OFFSET_WB_RF_RX_MANUAL2_REG56

#define OFFSET_WB_RF_RX_MANUAL2_REG56   56

OFFSET_WB_RF_RX_MANUAL3_REG57

#define OFFSET_WB_RF_RX_MANUAL3_REG57   57

OFFSET_WB_RF_RX_MIX_TIA_MUX1_REG85

#define OFFSET_WB_RF_RX_MIX_TIA_MUX1_REG85   85

OFFSET_WB_RF_RX_MIX_TIA_MUX2_REG86

#define OFFSET_WB_RF_RX_MIX_TIA_MUX2_REG86   86

OFFSET_WB_RF_RX_MIX_TIA_MUX3_REG87

#define OFFSET_WB_RF_RX_MIX_TIA_MUX3_REG87   87

OFFSET_WB_RF_RX_MIX_TIA_MUX4_REG88

#define OFFSET_WB_RF_RX_MIX_TIA_MUX4_REG88   88

OFFSET_WB_RF_RX_SETUP_REG53

#define OFFSET_WB_RF_RX_SETUP_REG53   53

OFFSET_WB_RF_RX_TOP_TEST_REG13

#define OFFSET_WB_RF_RX_TOP_TEST_REG13   13

OFFSET_WB_RF_TRX_IQCAL_CONTROL_REG25

#define OFFSET_WB_RF_TRX_IQCAL_CONTROL_REG25   25

OFFSET_WB_RF_TRX_SWAP_REG26

#define OFFSET_WB_RF_TRX_SWAP_REG26   26

OFFSET_WB_RF_TX_PA_VB_LUT_REG133

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG133   133

OFFSET_WB_RF_TX_PA_VB_LUT_REG134

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG134   134

OFFSET_WB_RF_TX_PA_VB_LUT_REG135

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG135   135

OFFSET_WB_RF_TX_PA_VB_LUT_REG142

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG142   142

OFFSET_WB_RF_TX_PA_VB_LUT_REG143

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG143   143

OFFSET_WB_RF_TX_PA_VB_LUT_REG144

#define OFFSET_WB_RF_TX_PA_VB_LUT_REG144   144

OFFSET_WB_RF_TX_RC_CODE2_REG24

#define OFFSET_WB_RF_TX_RC_CODE2_REG24   24

OFFSET_WB_RFABB_LPF_BW_MAP_REG27

#define OFFSET_WB_RFABB_LPF_BW_MAP_REG27   27

OFFSET_WB_TEST_MUX_SWITCH_REG19

#define OFFSET_WB_TEST_MUX_SWITCH_REG19   19

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG129

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG129   129

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG130

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG130   130

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG131

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG131   131

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG132

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG132   132

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG138

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG138   138

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG139

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG139   139

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG140

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG140   140

OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG141

#define OFFSET_WB_TX_PA_ADB_IOUT_LUT_REG141   141

OFFSET_WB_TX_PA_TRIM_MANUAL_REG100

#define OFFSET_WB_TX_PA_TRIM_MANUAL_REG100   100

OFFSET_WB_TX_PA_TRIM_MANUAL_REG101

#define OFFSET_WB_TX_PA_TRIM_MANUAL_REG101   101

OFFSET_WB_TX_PA_TRIM_MANUAL_REG102

#define OFFSET_WB_TX_PA_TRIM_MANUAL_REG102   102

OFFSET_WB_TX_RF_CALIBRATION_REG98

#define OFFSET_WB_TX_RF_CALIBRATION_REG98   98

OFFSET_WB_TX_RF_CONFIG_REG97

#define OFFSET_WB_TX_RF_CONFIG_REG97   97

OFFSET_WB_TX_TRIM_BIAS_MANUAL_REG103

#define OFFSET_WB_TX_TRIM_BIAS_MANUAL_REG103   103

OFFSET_WB_TX_TRIM_BIAS_MODE_REG99

#define OFFSET_WB_TX_TRIM_BIAS_MODE_REG99   99

OFFSET_WL_RF_TRX_RC_CODE1_REG20

#define OFFSET_WL_RF_TRX_RC_CODE1_REG20   20

OFFSET_WL_RF_TRX_RC_CODE1_REG21

#define OFFSET_WL_RF_TRX_RC_CODE1_REG21   21

OFFSET_WL_TX_PDET2G_CTRL_REG128

#define OFFSET_WL_TX_PDET2G_CTRL_REG128   128

OFFSET_WL_TX_PDET2G_CTRL_REG148

#define OFFSET_WL_TX_PDET2G_CTRL_REG148   148

类型定义说明

fe_hal_rf_2g_band_sel_enum_uint8

typedef osal_u8 fe_hal_rf_2g_band_sel_enum_uint8

fe_hal_rf_ctune_val_index_enum_uint8

typedef osal_u8 fe_hal_rf_ctune_val_index_enum_uint8

fe_hal_rf_reg_type_enum_uint8

typedef osal_u8 fe_hal_rf_reg_type_enum_uint8

枚举类型说明

fe_hal_rf_2g_band_sel_enum

enum fe_hal_rf_2g_band_sel_enum

枚举值
CALI_RF_2G_BAND_SEL_1
CALI_RF_2G_BAND_SEL_2
CALI_RF_2G_BAND_SEL_3
CALI_RF_2G_BAND_SEL_BUTT

fe_hal_rf_ctune_val_index_enum

enum fe_hal_rf_ctune_val_index_enum

枚举值
CALI_RF_CTUNE_VAL_INDEX_0
CALI_RF_CTUNE_VAL_INDEX_1
CALI_RF_CTUNE_VAL_INDEX_2
CALI_RF_CTUNE_VAL_INDEX_3
CALI_RF_CTUNE_VAL_INDEX_4
CALI_RF_CTUNE_VAL_INDEX_5
CALI_RF_CTUNE_VAL_INDEX_6
CALI_RF_CTUNE_VAL_INDEX_7
CALI_RF_CTUNE_VAL_INDEX_BUTT

fe_hal_rf_reg_type_enum

enum fe_hal_rf_reg_type_enum

枚举值
RF_REG
PLL_REG
SOC_REG
REG_BUTT

函数说明

hal_rf_get_fb_gain_lna_lut()

osal_u8 hal_rf_get_fb_gain_lna_lut

(

osal_u8

fb_gain_local

)

hal_rf_get_soc_reg_base()

osal_u32 hal_rf_get_soc_reg_base

(

osal_u8

rf_id

)

hal_rf_set_abb2_d_wb_ppa_code_gm_local()

osal_void hal_rf_set_abb2_d_wb_ppa_code_gm_local

(

osal_u16

ppa_code_gm

)

hal_rf_set_abb2_d_wb_ppa_code_unit_local()

osal_void hal_rf_set_abb2_d_wb_ppa_code_unit_local

(

osal_u16

ppa_code_unit

)

hal_rf_set_pll1_reg()

osal_void hal_rf_set_pll1_reg

(

osal_u16

pll_top

)

hal_rf_set_pll2_reg()

osal_void hal_rf_set_pll2_reg

(

osal_u16

div_int

)

hal_soc_cfg_dac_index_man()

osal_void hal_soc_cfg_dac_index_man

(

osal_u16

dac_index

)