WS63 SDK 文档 7021f4f@fbb_ws63
ws63 和 ws63e 解决方案的 SDK 文档
载入中...
搜索中...
未找到
sio_porting.c 文件参考
#include "common_def.h"
#include "hal_sio_v151.h"
#include "oal_interface.h"
#include "soc_osal.h"
#include "pinctrl_porting.h"
#include "pinctrl.h"
#include "chip_core_irq.h"
#include "sio_porting.h"
#include "debug_print.h"
sio_porting.c 的引用(Include)关系图:

结构体

struct  sio_interrupt
 

宏定义

#define FREQ_OD_NEED   32
 
#define I2S_MCLK_DIV   2
 
#define I2S_MCLK_RATE   12288
 
#define I2S_BUS_0_REAL_BASE   (I2S_BUS_0_BASE_ADDR - 0x3c)
 
#define I2S_MERGE_TX_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0xc0)
 
#define I2S_MERGE_RX_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0xa0)
 
#define I2S_TX_SPLIT_LEFT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x4c)
 
#define I2S_TX_SPLIT_RIGHT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x50)
 
#define I2S_RX_SPLIT_LEFT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x54)
 
#define I2S_RX_SPLIT_RIGHT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x58)
 
#define HAL_I2S_CLK_CG_ADDR   0x44001100
 
#define CMU_NEW_CFG0   0x400034a0
 
#define HAL_I2S_CLK_CG_ON   0xffffffff
 
#define I2S_CLKEN_BIT   12
 
#define I2S_BUS_CLKEN_BIT   11
 
#define CMU_DIV_AD_RSTN_SYNC_BIT   0
 

类型定义

typedef struct sio_interrupt sio_interrupt_t
 

函数

uintptr_t sio_porting_base_addr_get (sio_bus_t bus)
 Get the base address of a specified sio.
 
void sio_porting_register_hal_funcs (sio_bus_t bus)
 Register hal funcs objects into hal_sio module.
 
void sio_porting_unregister_hal_funcs (sio_bus_t bus)
 Unregister hal funcs objects from hal_sio module.
 
void sio_porting_register_irq (sio_bus_t bus)
 Register the interrupt of sio.
 
void sio_porting_unregister_irq (sio_bus_t bus)
 Unregister the interrupt of sio.
 
void irq_sio0_handler (void)
 The interrupt handler of sio0.
 
void sio_porting_clock_enable (bool enable)
 SIO clock.
 
void sio_porting_i2s_pinmux (void)
 Config the pin mode.
 
uintptr_t i2s_porting_tx_merge_data_addr_get (sio_bus_t bus)
 
uintptr_t i2s_porting_rx_merge_data_addr_get (sio_bus_t bus)
 
uintptr_t i2s_porting_tx_left_data_addr_get (sio_bus_t bus)
 
uintptr_t i2s_porting_tx_right_data_addr_get (sio_bus_t bus)
 
uintptr_t i2s_porting_rx_left_data_addr_get (sio_bus_t bus)
 
uintptr_t i2s_porting_rx_right_data_addr_get (sio_bus_t bus)
 
uint32_t sio_porting_get_bclk_div_num (uint8_t data_width, uint32_t ch)
 get bclk.
 
uint32_t sio_porting_get_mclk (void)
 get mclk.
 

宏定义说明

◆ CMU_DIV_AD_RSTN_SYNC_BIT

#define CMU_DIV_AD_RSTN_SYNC_BIT   0

◆ CMU_NEW_CFG0

#define CMU_NEW_CFG0   0x400034a0

◆ FREQ_OD_NEED

#define FREQ_OD_NEED   32

Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2023-2023. All rights reserved.

Description: Provides i2s port
History:
2023-03-10, Create file.

◆ HAL_I2S_CLK_CG_ADDR

#define HAL_I2S_CLK_CG_ADDR   0x44001100

◆ HAL_I2S_CLK_CG_ON

#define HAL_I2S_CLK_CG_ON   0xffffffff

◆ I2S_BUS_0_REAL_BASE

#define I2S_BUS_0_REAL_BASE   (I2S_BUS_0_BASE_ADDR - 0x3c)

◆ I2S_BUS_CLKEN_BIT

#define I2S_BUS_CLKEN_BIT   11

◆ I2S_CLKEN_BIT

#define I2S_CLKEN_BIT   12

◆ I2S_MCLK_DIV

#define I2S_MCLK_DIV   2

◆ I2S_MCLK_RATE

#define I2S_MCLK_RATE   12288

◆ I2S_MERGE_RX_DATA_ADDR

#define I2S_MERGE_RX_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0xa0)

◆ I2S_MERGE_TX_DATA_ADDR

#define I2S_MERGE_TX_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0xc0)

◆ I2S_RX_SPLIT_LEFT_DATA_ADDR

#define I2S_RX_SPLIT_LEFT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x54)

◆ I2S_RX_SPLIT_RIGHT_DATA_ADDR

#define I2S_RX_SPLIT_RIGHT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x58)

◆ I2S_TX_SPLIT_LEFT_DATA_ADDR

#define I2S_TX_SPLIT_LEFT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x4c)

◆ I2S_TX_SPLIT_RIGHT_DATA_ADDR

#define I2S_TX_SPLIT_RIGHT_DATA_ADDR   (I2S_BUS_0_REAL_BASE + 0x50)

类型定义说明

◆ sio_interrupt_t