This union represents the bit fields in the Receive FIFO Level Register.
Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_spi_v151_regs_def.h>

成员变量
uint32_t	d32

struct {

uint32_t dcfe_tfee: 1

uint32_t reserved1_3: 3

uint32_t rfne: 1

uint32_t rffe: 1

uint32_t reserved6_10: 5

uint32_t tfnf: 1

uint32_t tfe: 1

uint32_t reserved13_14: 2

uint32_t sbf: 1

uint32_t reserved16_31

}	b

详细描述

This union represents the bit fields in the Receive FIFO Level Register.
Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

◆ [struct]

struct { ... } spi_wsr_data::b

Register bits.

◆ d32

uint32_t spi_wsr_data::d32

Raw register data.

◆ dcfe_tfee

uint32_t spi_wsr_data::dcfe_tfee

Data Collision Error.
Relevant only when the spi is configured as a master device. This bit will be set if ss_in_n input is asspi_slenrted by other master, when the spi master is in the middle of the transfer. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read.
Values:

0x0 (NO_ERROR_CONDITION): No Error
0x1 (TX_COLLISION_ERROR): Transmit Data Collision Error

◆ reserved13_14

uint32_t spi_wsr_data::reserved13_14

◆ reserved16_31

uint32_t spi_wsr_data::reserved16_31

◆ reserved1_3

uint32_t spi_wsr_data::reserved1_3

◆ reserved6_10

uint32_t spi_wsr_data::reserved6_10

◆ rffe

uint32_t spi_wsr_data::rffe

Receive FIFO Full.
When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared.
Values:

0x0 (NOT_FULL): Receive FIFO is not full
0x1 (FULL): Receive FIFO is full

◆ rfne

uint32_t spi_wsr_data::rfne

Receive FIFO Not Empty.
Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO.
Values:

0x0 (EMPTY): Receive FIFO is empty
0x1 (NOT_EMPTY): Receive FIFO is not empty

◆ sbf

uint32_t spi_wsr_data::sbf

SPI Busy Flag.
When set, indicates that a spi_slenrial transfer is in progress; when cleared indicates that the spi is idle or disabled.
Values:

0x0 (INACTIVE): spi is idle or disabled
0x1 (ACTIVE): spi is actively transferring data

◆ tfe

uint32_t spi_wsr_data::tfe

Transmit FIFO Empty.
When the transmit FIFO is completely empty, this bit is set.
When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt.
Values:

0x0 (NOT_EMPTY): Transmit FIFO is not empty
0x1 (EMPTY): Transmit FIFO is empty

◆ tfnf

uint32_t spi_wsr_data::tfnf

Transmit FIFO Not Full.
Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full.
Values:

0x0 (FULL): Transmit FIFO is full
0x1 (NOT_FULL): Transmit FIFO is not Full

该联合体的文档由以下文件生成:

src/drivers/drivers/hal/spi/v151/hal_spi_v151_regs_def.h