spi_twlr_data联合体 参考

This union represents the bit fields in the Transmit FIFO Threshold Level.
Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_spi_v151_regs_def.h>

成员变量
uint32_t	d32
struct {
uint32_t   twl
}	b

详细描述

This union represents the bit fields in the Transmit FIFO Threshold Level.
Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

[struct]

struct { ... } spi_twlr_data::b

Register bits.

d32

uint32_t spi_twlr_data::d32

Raw register data.

twl

uint32_t spi_twlr_data::twl

Transmit FIFO Threshold.
Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256; this register is sized to the number of address bits needed to access the FIFO. If you attempt to set this value greater than or equal to the depth of the FIFO, this field is not written and retains its current value. When the number of transmit FIFO entries is less than or equal to this value, the transmit FIFO empty interrupt is triggered. For information on the Transmit FIFO Threshold values, see the "Master SPI and SSP Serial Transfers" in the spi Databook.
ssi_txe_intr is asspi_slenrted when TFT or less data entries are present in transmit FIFO.

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该联合体的文档由以下文件生成:

• src/drivers/drivers/hal/spi/v151/hal_spi_v151_regs_def.h