This union represents the bit fields in the SPI Control 0 Register.
Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_spi_v151_regs_def.h>

成员变量
uint32_t	d32

struct {

uint32_t waitnum: 5

uint32_t aaitf: 2

uint32_t rdsen: 1

uint32_t addrlen: 4

uint32_t ilen: 2

uint32_t iddren: 1

uint32_t ddren: 1

uint32_t reserved16_31: 18

}	b

详细描述

This union represents the bit fields in the SPI Control 0 Register.
Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

◆ aaitf

uint32_t spi_enhctl_data::aaitf

Address and instruction transfer format.
Selects whether spi will transmit instruction/address either in Standard SPI mode or the SPI mode selected in CTRLR0.SPI_FRF field. 00 - Instruction and Address will be sent in Standard SPI Mode. 01 - Instruction will be sent in Standard SPI Mode and Address will be sent in the mode specified by CTRLR0.SPI_FRF.
10 - Both Instruction and Address will be sent in the mode specified by SPI_FRF. 11 - reserved.

◆ addrlen

uint32_t spi_enhctl_data::addrlen

Address Length.
This bit defines Length of Address to be transmitted. Only after this much bits are programmed in to the FIFO the transfer can begin. For information on the ADDR_Ldecode value, see "Read Operation in Enhanced SPI Modes" section in the spi Databook.
Values:

0x0 (ADDR_L_0): 0-bit Address Width
0x1 (ADDR_L_1): 4-bit Address Width
0x2 (ADDR_L_2): 8-bit Address Width
0x3 (ADDR_L_3): 12-bit Address Width
0x4 (ADDR_L_4): 16-bit Address Width
0x5 (ADDR_L_5): 20-bit Address Width
0x6 (ADDR_L_6): 24-bit Address Width
0x7 (ADDR_L_7): 28-bit Address Width
0x8 (ADDR_L_8): 32-bit Address Width
0x9 (ADDR_L_9): 36-bit Address Width
0xa (ADDR_L_10): 40-bit Address Width
0xb (ADDR_L_11): 44-bit Address Width
0xc (ADDR_L_12): 48-bit Address Width
0xd (ADDR_L_13): 52-bit Address Width
0xe (ADDR_L_14): 56-bit Address Width
0xf (ADDR_L_15): 60-bit Address Width

◆ [struct]

struct { ... } spi_enhctl_data::b

Register bits.

◆ d32

uint32_t spi_enhctl_data::d32

Raw register data.

◆ ddren

uint32_t spi_enhctl_data::ddren

SPI DDR Enable bit.
This will enable Dual-data rate transfers in Dual/Quad/Octal frame formats of SPI.

◆ iddren

uint32_t spi_enhctl_data::iddren

Instruction DDR Enable bit.
This will enable Dual-data rate transfer for Instruction phase.

◆ ilen

uint32_t spi_enhctl_data::ilen

Instruction Length.
Dual/Quad/Octal mode instruction length in bits.
Values:

0x0 (INST_L_0): 0-bit (No Instruction)
0x1 (INST_L_1): 4-bit Instruction
0x2 (INST_L_2): 8-bit Instruction
0x3 (INST_L_3): 16-bit Instruction

◆ rdsen

uint32_t spi_enhctl_data::rdsen

Read data strobe enable bit.
Once this bit is set to 1 spi will use Read data strobe (rxds) to capture read data in DDR mode.

◆ reserved16_31

uint32_t spi_enhctl_data::reserved16_31

◆ waitnum

uint32_t spi_enhctl_data::waitnum

Wait cycles.
Number of wait cycles in Dual/Quad/Octal mode between control frames transmit and data reception. This value is specified as number of SPI clock cycles. For information on the WAIT_CYCLES decode value, see "Read Operation in Enhanced SPI Modes" section in the spi Databook.

该联合体的文档由以下文件生成:

src/drivers/drivers/hal/spi/v151/hal_spi_v151_regs_def.h