bus_config2联合体 参考

This union represents the bit fields in the SFC bus config Register 2.
Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_sfc_v150_regs_def.h>

成员变量
uint32_t	d32
struct {
uint32_t   wip_locate: 3
uint32_t   bus_ddr_mode: 1
uint32_t   ddr_rd_dummy_bytes: 4
uint32_t   ddr_wr_dummy_bytes: 4
uint32_t   sfc_ddr_tx_delay_enable: 1
uint32_t   reserved: 19
}	b
struct {
uint32_t   wip_locate: 3
uint32_t   bus_ddr_mode: 1
uint32_t   ddr_rd_dummy_bytes: 4
uint32_t   ddr_wr_dummy_bytes: 4
uint32_t   sfc_ddr_tx_delay_enable: 1
uint32_t   reserved: 19
}	b

详细描述

This union represents the bit fields in the SFC bus config Register 2.
Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

[struct] [1/2]

struct { ... } bus_config2::b

Register bits.

[struct] [2/2]

struct { ... } bus_config2::b

Register bits.

bus_ddr_mode

uint32_t bus_config2::bus_ddr_mode

DDR mode enable.

d32

uint32_t bus_config2::d32

Raw register data.

ddr_rd_dummy_bytes

uint32_t bus_config2::ddr_rd_dummy_bytes

Number of dummy bytes in the read operation in DDR mode.

ddr_wr_dummy_bytes

uint32_t bus_config2::ddr_wr_dummy_bytes

Number of dummy bytes in the write operation in DDR mode.

reserved

uint32_t bus_config2::reserved

sfc_ddr_tx_delay_enable

uint32_t bus_config2::sfc_ddr_tx_delay_enable

Phase relationship between CLK and TX_DATA in DDR mode: value :0: align; 1: CLK is 1/4 SFC_CLK cycle ahead of TX_DATA.

wip_locate

uint32_t bus_config2::wip_locate

Write In Progress is located in the flash status register.

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该联合体的文档由以下文件生成:

• src/drivers/chips/ws63/rom/drivers/drivers/hal/sfc/hal_sfc_v150_regs_def.h
• src/drivers/drivers/hal/sfc/hal_sfc_v150_regs_def.h