global_config联合体 参考

This union represents the bit fields in the SFC global config Register.
Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_sfc_v150_regs_def.h>

成员变量
uint32_t	d32
struct {
uint32_t   mode: 1
uint32_t   wp_en: 1
uint32_t   flash_addr_mode: 1
uint32_t   rd_delay: 3
uint32_t   sample_test: 4
uint32_t   reserved: 22
}	b
struct {
uint32_t   mode: 1
uint32_t   wp_en: 1
uint32_t   flash_addr_mode: 1
uint32_t   rd_delay: 3
uint32_t   sample_test: 4
uint32_t   reserved: 22
}	b

详细描述

This union represents the bit fields in the SFC global config Register.
Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

[struct] [1/2]

struct { ... } global_config::b

Register bits.

[struct] [2/2]

struct { ... } global_config::b

Register bits.

d32

uint32_t global_config::d32

Raw register data.

flash_addr_mode

uint32_t global_config::flash_addr_mode

SPI address mode.
Values:

• 0x0 3-byte addressing mode (default value)
• 0x1 4-byte addressing mode.

mode

uint32_t global_config::mode

SPI Mode.
Values:

• 0x0 SPI Mode0.
• 0x1 SPI Mode3.

rd_delay

uint32_t global_config::rd_delay

Number of delay cycles for reading data.
Values:

• 000: 0.5–1 clock cycle (default value)
• 001: 1–1.5 clock cycles;
• 010: 1.5–2 clock cycles;
• 011: 2–2.5 clock cycles;
• 100: 2.5–3 clock cycles;
• 101: 3–3.5 clock cycles;
• 110: 3.5–4 clock cycles;
• 111: not supported (processed according to "110").

reserved

uint32_t global_config::reserved

sample_test

uint32_t global_config::sample_test

In DDR mode, the sampling point is selected based on the delay parameters of different components.

wp_en

uint32_t global_config::wp_en

Hardware write protection enable.
Values:

• 0x0 disabled.
• 0x1 enabled.

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该联合体的文档由以下文件生成:

• src/drivers/chips/ws63/rom/drivers/drivers/hal/sfc/hal_sfc_v150_regs_def.h
• src/drivers/drivers/hal/sfc/hal_sfc_v150_regs_def.h