This union represents the bit fields in the Control Register. Read the register into the d32 member then set/clear the bits using the b elements. 更多...

#include <hal_watchdog_v151_regs_def.h>

成员变量
uint32_t	d32

struct {

uint32_t wdt_en: 1

uint32_t reserved1: 1

uint32_t rst_en: 1

uint32_t rst_pl: 3

uint32_t wdt_imsk: 1

uint32_t wdt_mode: 1

uint32_t reserved8_31: 24

}	b

struct {

uint32_t wdt_en: 1

uint32_t reserved1: 1

uint32_t rst_en: 1

uint32_t rst_pl: 3

uint32_t wdt_imsk: 1

uint32_t wdt_mode: 1

uint32_t reserved8_31: 24

}	b

详细描述

This union represents the bit fields in the Control Register. Read the register into the d32 member then set/clear the bits using the b elements.

结构体成员变量说明

◆ [struct] [1/2]

struct { ... } wdt_v151_cr_data::b

◆ [struct] [2/2]

struct { ... } wdt_v151_cr_data::b

◆ d32

uint32_t wdt_v151_cr_data::d32

◆ reserved1

uint32_t wdt_v151_cr_data::reserved1

◆ reserved8_31

uint32_t wdt_v151_cr_data::reserved8_31

◆ rst_en

uint32_t wdt_v151_cr_data::rst_en

System reset signal generation enable register. Cannot generate a reset signal(0), Can generate a reset signal(1).

◆ rst_pl

uint32_t wdt_v151_cr_data::rst_pl

System reset signal effective length configuration register. -3'b000: Valid length of the system reset signal is 8'h2, -3'b001: Valid length of the system reset signal is 8'h4, -3'b010: Valid length of the system reset signal is 8'h8, -3'b011: Valid length of the system reset signal is 8'h10, -3'b100: Valid length of the system reset signal is 8'h20, -3'b101: Valid length of the system reset signal is 8'h40, -3'b110: Valid length of the system reset signal is 8'h80, -3'b111: Valid length of the system reset signal is 8'h100.

◆ wdt_en

uint32_t wdt_v151_cr_data::wdt_en

Enable register for counter operation. Counter Unenable(0), Counter Enable(1).

◆ wdt_imsk

uint32_t wdt_v151_cr_data::wdt_imsk

Interrupt block Register. -1'b0: No interruption blocking, -1'b1: interruption blocking.

◆ wdt_mode

uint32_t wdt_v151_cr_data::wdt_mode

wdt working mode configuration register. -1'b0: One interrupt to generate a reset signal, -1'b1: Two interrupt to generate a reset signal.

该联合体的文档由以下文件生成:

src/drivers/chips/ws63/rom/drivers/drivers/hal/watchdog/v151/hal_watchdog_v151_regs_def.h
src/drivers/drivers/hal/watchdog/v151/hal_watchdog_v151_regs_def.h