9#ifndef REBOOT_PORTING_H
10#define REBOOT_PORTING_H
18#define HAL_REBOOT_REASON_MCPU_WDT 0x2002
19#define HAL_REBOOT_REASON_DSP_WDT 0x4002
20#define HAL_REBOOT_REASON_BCPU_WDT 0x8002
21#define HAL_REBOOT_REASON_BCPU_CHIP_WDT 0x8004
23#if MASTER_BY_WS53_ONLY
24#define HAL_CHIP_RESET_REG (ULP_AON_CTL_RB_ADDR + CHIP_RESET_OFF)
26#define HAL_CHIP_RESET_REG (GLB_CTL_M_RB_BASE + CHIP_RESET_OFF)
29#define HAL_CHIP_RESET_REG_OFFSET 0x0
30#define HAL_CHIP_RESET_REG_ENABLE_RESET_BIT 2
32#define HAL_PMU_PROTECT_STATUS_REG (PMU1_CTL_RB_BASE + 0x370)
33#define HAL_PMU_PROTECT_STATUS_CLR_REG (PMU1_CTL_RB_BASE + 0x370)
36#define HAL_PMU_PROTECT_BUCK2_SCP_BIT 2
37#define HAL_PMU_PROTECT_BUCK1_SCP_BIT 3
38#define HAL_PMU_PROTECT_CHIP_WDG_BIT 4
39#define HAL_PMU_PROTECT_CHIP_WDG_BIT_CLR 0
41#define HAL_BCPU_RESET_STS_REG (GLB_CTL_M_RB_BASE + 0x30)
42#define HAL_MCPU_RESET_STS_REG (GLB_CTL_M_RB_BASE + 0x34)
45#define HAL_DSP_RESET_STS_REG (GLB_CTL_B_RB_BASE + 0x38)
46#define HAL_RESET_STS_COMMON_RESET_BIT 0
47#define HAL_RESET_STS_CORE_RESET_BIT 1
48#define HAL_RESET_STS_CORE_WDT_RESET_BIT 2
49#define HAL_RESET_STS_CLEAR_REG (GLB_CTL_M_RB_BASE + 0x3c)
50#define HAL_RESET_STS_CLEAR_ALL 0xFF
53#define HAL_ULP_AON_GENERAL_REG (ULP_AON_CTL_RB_ADDR + 0x14)
55#define HAL_ULP_AON_NO_POWEROFF_FLAG 0xA5A5
reboot_port_rst_reason
Definition reboot_porting.h:63
void reboot_mem_save_to_flash(void)
void reboot_port_reboot_chip(void)
Definition reboot_porting.c:82
enum reboot_port_rst_reason reboot_port_rst_reason_t
uint32_t reboot_port_get_rst_reason(void)
Definition reboot_porting.c:93
void reboot_mem_flash_erase(void)
@ RST_REASON_WDT_RST
Definition reboot_porting.h:64
@ RST_REASON_SOFT_RST
Definition reboot_porting.h:65
@ RST_REASON_HARD_RST
Definition reboot_porting.h:66
@ RST_REASON_INVALID
Definition reboot_porting.h:67