spi_v151_regs结构体 参考

Registers associated with spi. 更多...

#include <hal_spi_v151_regs_def.h>

成员变量
volatile uint32_t	spi_er
volatile uint32_t	spi_ctra
volatile uint32_t	spi_ctrb
volatile uint32_t	spi_enhctl
volatile uint32_t	spi_mcr
volatile uint32_t	spi_brs
volatile uint32_t	spi_dcr
volatile uint32_t	spi_drdl
volatile uint32_t	spi_dtdl
volatile uint32_t	spi_rsdr
volatile uint32_t	spi_tder
volatile uint32_t	spi_drnm [36]
volatile uint32_t	spi_rainsr
volatile uint32_t	spi_insr
volatile uint32_t	spi_inmar
volatile uint32_t	spi_slenr
volatile uint32_t	spi_twlr
volatile uint32_t	spi_tlr
volatile uint32_t	spi_tfoficr
volatile uint32_t	spi_rwlr
volatile uint32_t	spi_rlr
volatile uint32_t	spi_rfficr
volatile uint32_t	spi_wsr
volatile uint32_t	spi_msticr
volatile uint32_t	spi_id
volatile uint32_t	spi_rsvd
volatile uint32_t	spi_rxoicr
volatile uint32_t	spi_icr

详细描述

Registers associated with spi.

结构体成员变量说明

spi_brs

volatile uint32_t spi_v151_regs::spi_brs

This register is valid only when the spi is configured as a master device. When the spi... Offset: 14h.

spi_ctra

volatile uint32_t spi_v151_regs::spi_ctra

This register controls the spi_slenrial data transfer. It is impossible to write to this register when... Offset: 04h.

spi_ctrb

volatile uint32_t spi_v151_regs::spi_ctrb

This register exists only when the spi is configured as a master device. When the spi... Offset: 08h.

spi_dcr

volatile uint32_t spi_v151_regs::spi_dcr

This register is only valid when spi is configured with a set of DMA Controller interface... Offset: 18h.

spi_drdl

volatile uint32_t spi_v151_regs::spi_drdl

This register is only valid when spi is configured with a set of DMA interface signals... Offset: 1Ch.

spi_drnm

volatile uint32_t spi_v151_regs::spi_drnm[36]

The spi data register is a 16/32-bit (depending on MAX_XFER_SIZE) read/write buffer for the... Offset: 2Ch.

spi_dtdl

volatile uint32_t spi_v151_regs::spi_dtdl

This register is only valid when the spi is configured with a set of DMA interface signals... Offset: 20h.

spi_enhctl

volatile uint32_t spi_v151_regs::spi_enhctl

This register is valid only when SPI_MODE is either set to "Dual" or "Quad" or "Octal" mode. This... Offset: 0Ch.

spi_er

volatile uint32_t spi_v151_regs::spi_er

This register enables and disables the spi. Reset Value: 0x0 Offset: 00h.

spi_icr

volatile uint32_t spi_v151_regs::spi_icr

Interrupt Clear Register. Reset Value: 0x0 Offset: F8h.

spi_id

volatile uint32_t spi_v151_regs::spi_id

This read-only register stores the specific spi component version. Reset Value:... Offset: ECh.

spi_inmar

volatile uint32_t spi_v151_regs::spi_inmar

This read/write reigster masks or enables all interrupts generated by the spi. When the spi... Offset: C4h.

spi_insr

volatile uint32_t spi_v151_regs::spi_insr

This register reports the status of the spi interrupts after they have been masked. Reset... Offset: C0h.

spi_mcr

volatile uint32_t spi_v151_regs::spi_mcr

This register controls the direction of the data word for the half-duplex Microwire spi_slenrial protocol... Offset: 10h.

spi_msticr

volatile uint32_t spi_v151_regs::spi_msticr

Multi-Master Interrupt Clear Register. Reset Value: 0x0 Offset: E8h.

spi_rainsr

volatile uint32_t spi_v151_regs::spi_rainsr

This read-only register reports the status of the spi interrupts prior to masking. Reset... Offset: BCh.

spi_rfficr

volatile uint32_t spi_v151_regs::spi_rfficr

Receive FIFO Underflow Interrupt Clear Register. Reset Value: 0x0 Offset: E0h.

spi_rlr

volatile uint32_t spi_v151_regs::spi_rlr

This register contains the number of valid data entries in the receive FIFO memory. This register... Offset: DCh.

spi_rsdr

volatile uint32_t spi_v151_regs::spi_rsdr

This register is only valid when the spi is configured with rxd sample delay logic.... Offset: 24h.

spi_rsvd

volatile uint32_t spi_v151_regs::spi_rsvd

Reserved. Offset: F0h.

spi_rwlr

volatile uint32_t spi_v151_regs::spi_rwlr

This register controls the threshold value for the receive FIFO memory. The spi is enabled... Offset: D8h.

spi_rxoicr

volatile uint32_t spi_v151_regs::spi_rxoicr

Receive FIFO Overflow Interrupt Clear Register. Reset Value: 0x0 Offset: F4h.

spi_slenr

volatile uint32_t spi_v151_regs::spi_slenr

This register is valid only when the spi is configured as a master device. When the spi... Offset: C8h.

spi_tder

volatile uint32_t spi_v151_regs::spi_tder

This Register is valid only when SPI_TDER is equal to 1. This register is used to control the... Offset: 28h.

spi_tfoficr

volatile uint32_t spi_v151_regs::spi_tfoficr

Transmit FIFO Overflow Interrupt Clear Register. Reset Value: 0x0 Offset: D4h.

spi_tlr

volatile uint32_t spi_v151_regs::spi_tlr

This register contains the number of valid data entries in the transmit FIFO memory. Reset Value:.. Offset: D0h.

spi_twlr

volatile uint32_t spi_v151_regs::spi_twlr

This register controls the threshold value for the transmit FIFO memory. The spi is enabled... Offset: CCh.

spi_wsr

volatile uint32_t spi_v151_regs::spi_wsr

This is a read-only register used to indicate the current transfer status, FIFO status, and any... Offset: E4h.

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该结构体的文档由以下文件生成:

• src/drivers/drivers/hal/spi/v151/hal_spi_v151_regs_def.h