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This union represents the bit fields in the Control Register 0.
Read the register into the d32 member then set/clear the bits using the b elements.
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#include <hal_spi_v151_regs_def.h>
成员变量 | ||
| uint32_t | d32 | |
| struct { | ||
| uint32_t soe: 1 | ||
| uint32_t srlt: 1 | ||
| uint32_t ssn_te: 1 | ||
| uint32_t scph: 1 | ||
| uint32_t scpol: 1 | ||
| uint32_t cfs16: 4 | ||
| uint32_t dfs16: 4 | ||
| uint32_t dfs32: 5 | ||
| uint32_t trsm: 2 | ||
| uint32_t enhff: 2 | ||
| uint32_t prs: 2 | ||
| uint32_t reserved24_31: 6 | ||
| } | b | |
This union represents the bit fields in the Control Register 0.
Read the register into the d32 member then set/clear the bits using the b elements.
| struct { ... } spi_ctra_data::b |
Register bits.
| uint32_t spi_ctra_data::cfs16 |
Control Frame Size.
Selects the length of the control word for the Microwire frame format.
Values:
| uint32_t spi_ctra_data::d32 |
Raw register data.
| uint32_t spi_ctra_data::dfs16 |
Data Frame Size.
This register field is only valid when SPI_MAX_XFER_SIZE is configured to 16. If SPI_MAX_XFER_SIZE is configured to 32, then writing to this field will not have any effect.
Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded.
You must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data.
| uint32_t spi_ctra_data::dfs32 |
Data Frame Size.
in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SPI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receive FIFO zeropadded. You are responsible for making sure that transmit data is right-justified before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data.
| uint32_t spi_ctra_data::enhff |
SPI Frame Format.
Selects data frame format for Transmitting/Receiving the data Bits only valid when SPI_SPI_MODE is either set to "Dual" or "Quad" or "Octal" mode.
When SPI_SPI_MODE is configured for "Dual Mode", 10/11 combination is reserved.
When SPI_SPI_MODE is configured for "Quad Mode", 11 combination is reserved.
Values:
| uint32_t spi_ctra_data::prs |
Frame Format.
Selects which spi_slenrial protocol transfers the data.
Values:
| uint32_t spi_ctra_data::reserved24_31 |
| uint32_t spi_ctra_data::scph |
Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The spi_slenrial clock phase selects the relationship of the spi_slenrial clock with the slave select signal.
When SCPH = 0, data are captured on the first edge of the spi_slenrial clock. When SCPH = 1, the spi_slenrial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the spi_slenrial clock.
Values:
| uint32_t spi_ctra_data::scpol |
Serial Clock Polarity.
Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive spi_slenrial clock, which is held inactive when the spi master is not actively transferring data on the spi_slenrial bus.
Values:
| uint32_t spi_ctra_data::soe |
Slave Output Enable.
Relevant only when the spi is configured as a spi_slenrial-slave device. When configured as a spi_slenrial master, this bit field has no functionality. This bit enables or disables the setting of the ssi_oe_n output from the spi spi_slenrial slave. When SLV_OE = 1, the ssi_oe_n output can never be active. When the ssi_oe_n output controls the tri-state buffer on the txd output from the slave, a high impedance state is always present on the slave txd output when SLV_OE = 1.
This is useful when the master transmits in broadcast mode (master transmits data to all slave devices). Only one slave may respond with data on the master rxd line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used), if you do not want this device to respond with data.
Values:
| uint32_t spi_ctra_data::srlt |
Shift Register Loop.
Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input.
Can be used in both spi_slenrial-slave and spi_slenrial-master modes. When the spi is configured as a slave in loopback mode, the ss_in_n and ssi_clk signals must be provided by an external source. In this mode, the slave cannot generate these signals because there is nothing to which to loop back
Values:
| uint32_t spi_ctra_data::ssn_te |
Slave Select Toggle Enable.
When operating in SPI mode with clock phase (SCPH) set to 0, this register controls the behavior of the slave select line (ss_*_n) between data frames. If this register field is set to 1 the ss_*_n line will toggle between consecutive data frames, with the spi_slenrial clock (sclk) being held to its default value while ss_*_n is high; if this register field is set to 0 the ss_*_n will stay low and sclk will run continuously for the duration of the transfer.
| uint32_t spi_ctra_data::trsm |
Transfer Mode.
Selects the mode of transfer for spi_slenrial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid.
In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer.
In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer.
In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor.
In eeprom-read mode, receive data is not valid while control data is being transmitted. When all control data is sent to the EEPROM, receive data becomes valid and transmit data becomes invalid. All data in the transmit FIFO is considered control data in this mode. This transfer mode is only valid when the spi is configured as master device.
1.9.8