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WS63 SDK 文档 7021f4f@fbb_ws63
ws63 和 ws63e 解决方案的 SDK 文档
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This union represents the bit fields in the SFC timing Register.
Read the register into the d32 member then set/clear the bits using the b elements.
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#include <hal_sfc_v150_regs_def.h>
成员变量 | ||
| uint32_t | d32 | |
| struct { | ||
| uint32_t tshsl: 4 | ||
| uint32_t reserved0: 4 | ||
| uint32_t tcss: 3 | ||
| uint32_t reserved1: 1 | ||
| uint32_t tcsh: 3 | ||
| } | b | |
| struct { | ||
| uint32_t tshsl: 4 | ||
| uint32_t reserved0: 4 | ||
| uint32_t tcss: 3 | ||
| uint32_t reserved1: 1 | ||
| uint32_t tcsh: 3 | ||
| } | b | |
This union represents the bit fields in the SFC timing Register.
Read the register into the d32 member then set/clear the bits using the b elements.
| struct { ... } timing::b |
Register bits.
| struct { ... } timing::b |
Register bits.
| uint32_t timing::d32 |
Raw register data.
| uint32_t timing::reserved0 |
| uint32_t timing::reserved1 |
| uint32_t timing::tcsh |
CS hold time. Time = tcss + 1.
| uint32_t timing::tcss |
CS setup time. Time = tcss + 1.
| uint32_t timing::tshsl |
Sets the interval between two flash operations. Time interval = tshsl + 2.