CHIP ARM Core Specifics 的协作图:

宏定义
#define	BT 0

#define	PROTOCOL 1

#define	APPS 2

#define	GNSS 3

#define	SECURITY 4

#define	HIFI PROTOCOL

#define	WIFI 5

#define	CONTROL_CORE 6

#define	SENSOR 7

#define	CM3 0

#define	CM7 1

#define	RISCV31 2

#define	RISCV70 3

#define	RISCV32 4

#define	CHIP_LIBRA (TARGET_CHIP_LIBRA)

#define	CHIP_SOCMN1 (TARGET_CHIP_SOCMN1)

#define	CHIP_BS25 (TARGET_CHIP_BS25)

#define	CHIP_BRANDY (TARGET_CHIP_BRANDY)

#define	CHIP_SW39 (TARGET_CHIP_SW39)

#define	CHIP_SW21 (TARGET_CHIP_SW21)

#define	MASTER_BY_ALL APPS

#define	CORE_NUMS 1

#define	CPU_NUM 1

#define	OTHER_CPU_NUM (CPU_NUM - 1)

#define	MASTER_BY_LIBRA_ONLY (CHIP_LIBRA && (CORE == APPS))

#define	MASTER_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == APPS))

#define	MASTER_BY_BS25_ONLY (CHIP_BS25 && (CORE == APPS))

#define	MASTER_BY_BS20_ONLY (CHIP_BS20 && (CORE == APPS))

#define	MASTER_BY_BS21_ONLY (CHIP_BS21 && (CORE == APPS))

#define	MASTER_BY_BS21E_ONLY (CHIP_BS21E && (CORE == APPS))

#define	MASTER_BY_BS21A_ONLY (CHIP_BS21A && (CORE == APPS))

#define	MASTER_BY_BS22_ONLY (CHIP_BS22 && (CORE == APPS))

#define	MASTER_BY_BS26_ONLY (CHIP_BS26 && (CORE == APPS))

#define	MASTER_BY_BRANDY_ONLY (CHIP_BRANDY && (CORE == APPS))

#define	MASTER_BY_WS53_ONLY (CHIP_WS53 && (CORE == APPS))

#define	MASTER_BY_SW39_ONLY (CHIP_SW39 && (CORE == APPS))

#define	MASTER_BY_SW21_ONLY (CHIP_SW21 && (CORE == APPS))

#define	MASTER_ONLY

#define	MCU_ONLY

#define	SLAVE_BY_LIBRA_BT (CHIP_LIBRA && (CORE == BT))

#define	SLAVE_BY_LIBRA_GNSS (CHIP_LIBRA && (CORE == GNSS))

#define	SLAVE_BY_LIBRA_SECURITY (CHIP_LIBRA && (CORE == SECURITY))

#define	SLAVE_BY_LIBRA_ONLY (SLAVE_BY_LIBRA_BT \|\| SLAVE_BY_LIBRA_GNSS \|\| SLAVE_BY_LIBRA_SECURITY)

#define	SLAVE_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == BT))

#define	SLAVE_BY_SW39_BT (CHIP_SW39 && (CORE == BT))

#define	SLAVE_BY_BS25_ONLY (CHIP_BS25 && (CORE == BT))

#define	SLAVE_BY_BRANDY_BT (CHIP_BRANDY && (CORE == BT))

#define	SLAVE_BY_BRANDY_DSP (CHIP_BRANDY && (CORE == DSP))

#define	SLAVE_BY_BRANDY_ONLY (SLAVE_BY_BRANDY_BT \|\| SLAVE_BY_BRANDY_DSP)

#define	SLAVE_BY_WS53_ONLY (CHIP_WS53 && (CORE == CONTROL_CORE))

#define	CHIP_LIBRA_FPGA (CHIP_LIBRA && (LIBRA_CHIP_FPGA))

#define	CHIP_LIBRA_CS (CHIP_LIBRA && (LIBRA_CHIP_CS))

#define	CHIP_SOCMN1_FPGA (CHIP_SOCMN1 && (SOCMN1_CHIP_FPGA))

#define	CHIP_SOCMN1_V100 (CHIP_SOCMN1 && (SOCMN1_CHIP_V100))

#define	CHIP_SOCMN1_V200 (CHIP_SOCMN1 && (SOCMN1_CHIP_V200))

#define	CHIP_BS25_FPGA (CHIP_BS25 && (BS25_CHIP_FPGA))

#define	CHIP_BS25_V100 (CHIP_BS25 && (BS25_CHIP_V100))

#define	CHIP_BS20_FPGA (CHIP_BS20 && (FPGA))

#define	CHIP_BS20_V100 (CHIP_BS20 && (ASIC))

#define	CHIP_BS21_FPGA (CHIP_BS21 && (FPGA))

#define	CHIP_BS21_V100 (CHIP_BS21 && (ASIC))

#define	CHIP_BS21E_FPGA (CHIP_BS21E && (FPGA))

#define	CHIP_BS21E_V100 (CHIP_BS21E && (ASIC))

#define	CHIP_BS21A_FPGA (CHIP_BS21A && (FPGA))

#define	CHIP_BS21A_V100 (CHIP_BS21A && (ASIC))

#define	CHIP_BS22_FPGA (CHIP_BS22 && (FPGA))

#define	CHIP_BS22_V100 (CHIP_BS22 && (ASIC))

#define	CHIP_BS26_FPGA (CHIP_BS26 && (FPGA))

#define	CHIP_BS26_V100 (CHIP_BS26 && (ASIC))

#define	CHIP_WS63_FPGA (CHIP_WS63 && (FPGA))

#define	CHIP_WS63_V100 (CHIP_WS63 && (ASIC))

#define	CHIP_BRANDY_FPGA (CHIP_BRANDY && (BRANDY_CHIP_FPGA))

#define	CHIP_BRANDY_V100 (CHIP_BRANDY && (BRANDY_CHIP_V100))

#define	CHIP_SW39_FPGA (CHIP_SW39 && (SW39_CHIP_FPGA))

#define	CHIP_SW21_FPGA (CHIP_SW21 && (SW21_CHIP_FPGA))

#define	CHIP_SW21_V100 (CHIP_SW21 && (SW21_CHIP_V100))

#define	CHIP_WS53_FPGA (CHIP_WS53 && (FPGA))

#define	CHIP_WS53_V100 (CHIP_WS53 && (ASIC))

#define	CHIP_FPGA

#define	CHIP_SOCMN1_ASIC (CHIP_SOCMN1_V100 \|\| CHIP_SOCMN1_V200)

#define	CHIP_BS25_ASIC (CHIP_BS25_V100)

#define	CHIP_BS20_ASIC (CHIP_BS20_V100)

#define	CHIP_BS21_ASIC (CHIP_BS21_V100)

#define	CHIP_BS21E_ASIC (CHIP_BS21E_V100)

#define	CHIP_BS21A_ASIC (CHIP_BS21A_V100)

#define	CHIP_BS22_ASIC (CHIP_BS22_V100)

#define	CHIP_BS26_ASIC (CHIP_BS26_V100)

#define	CHIP_BRANDY_ASIC (CHIP_BRANDY_V100)

#define	CHIP_WS63_ASIC (CHIP_WS63_V100)

#define	CHIP_WS53_ASIC (CHIP_WS53_V100)

#define	CHIP_SW21_ASIC (CHIP_SW21_V100)

#define	CHIP_ASIC

详细描述

CHIP ARM Core Application Core Specifics

宏定义说明

◆ APPS

#define APPS 2

◆ BT

#define BT 0

◆ CHIP_ASIC

#define CHIP_ASIC

值:

                               (CHIP_LIBRA_CS || CHIP_SOCMN1_ASIC || \
                               CHIP_BS25_ASIC || CHIP_BRANDY_ASIC || \
                               CHIP_BS20_ASIC || CHIP_BS21_ASIC || \
                               CHIP_BS21A_ASIC || CHIP_BS22_ASIC || \
                               CHIP_BS26_ASIC || CHIP_WS63_ASIC || \
                               CHIP_WS53_ASIC || CHIP_SW21_ASIC || \
                               CHIP_BS21E_ASIC)

◆ CHIP_BRANDY

#define CHIP_BRANDY (TARGET_CHIP_BRANDY)

◆ CHIP_BRANDY_ASIC

#define CHIP_BRANDY_ASIC (CHIP_BRANDY_V100)

◆ CHIP_BRANDY_FPGA

#define CHIP_BRANDY_FPGA (CHIP_BRANDY && (BRANDY_CHIP_FPGA))

◆ CHIP_BRANDY_V100

#define CHIP_BRANDY_V100 (CHIP_BRANDY && (BRANDY_CHIP_V100))

◆ CHIP_BS20_ASIC

#define CHIP_BS20_ASIC (CHIP_BS20_V100)

◆ CHIP_BS20_FPGA

#define CHIP_BS20_FPGA (CHIP_BS20 && (FPGA))

◆ CHIP_BS20_V100

#define CHIP_BS20_V100 (CHIP_BS20 && (ASIC))

◆ CHIP_BS21_ASIC

#define CHIP_BS21_ASIC (CHIP_BS21_V100)

◆ CHIP_BS21_FPGA

#define CHIP_BS21_FPGA (CHIP_BS21 && (FPGA))

◆ CHIP_BS21_V100

#define CHIP_BS21_V100 (CHIP_BS21 && (ASIC))

◆ CHIP_BS21A_ASIC

#define CHIP_BS21A_ASIC (CHIP_BS21A_V100)

◆ CHIP_BS21A_FPGA

#define CHIP_BS21A_FPGA (CHIP_BS21A && (FPGA))

◆ CHIP_BS21A_V100

#define CHIP_BS21A_V100 (CHIP_BS21A && (ASIC))

◆ CHIP_BS21E_ASIC

#define CHIP_BS21E_ASIC (CHIP_BS21E_V100)

◆ CHIP_BS21E_FPGA

#define CHIP_BS21E_FPGA (CHIP_BS21E && (FPGA))

◆ CHIP_BS21E_V100

#define CHIP_BS21E_V100 (CHIP_BS21E && (ASIC))

◆ CHIP_BS22_ASIC

#define CHIP_BS22_ASIC (CHIP_BS22_V100)

◆ CHIP_BS22_FPGA

#define CHIP_BS22_FPGA (CHIP_BS22 && (FPGA))

◆ CHIP_BS22_V100

#define CHIP_BS22_V100 (CHIP_BS22 && (ASIC))

◆ CHIP_BS25

#define CHIP_BS25 (TARGET_CHIP_BS25)

◆ CHIP_BS25_ASIC

#define CHIP_BS25_ASIC (CHIP_BS25_V100)

◆ CHIP_BS25_FPGA

#define CHIP_BS25_FPGA (CHIP_BS25 && (BS25_CHIP_FPGA))

◆ CHIP_BS25_V100

#define CHIP_BS25_V100 (CHIP_BS25 && (BS25_CHIP_V100))

◆ CHIP_BS26_ASIC

#define CHIP_BS26_ASIC (CHIP_BS26_V100)

◆ CHIP_BS26_FPGA

#define CHIP_BS26_FPGA (CHIP_BS26 && (FPGA))

◆ CHIP_BS26_V100

#define CHIP_BS26_V100 (CHIP_BS26 && (ASIC))

◆ CHIP_FPGA

#define CHIP_FPGA

值:

                               (CHIP_LIBRA_FPGA || CHIP_SOCMN1_FPGA || CHIP_BS25_FPGA || CHIP_SW39_FPGA || \
                               CHIP_BRANDY_FPGA || CHIP_BS20_FPGA || CHIP_BS21_FPGA || CHIP_BS21A_FPGA || \
                               CHIP_BS22_FPGA || CHIP_BS26_FPGA || CHIP_WS63_FPGA || CHIP_WS53_FPGA || \
                               CHIP_SW21_FPGA || CHIP_BS21E_FPGA)

◆ CHIP_LIBRA

#define CHIP_LIBRA (TARGET_CHIP_LIBRA)

◆ CHIP_LIBRA_CS

#define CHIP_LIBRA_CS (CHIP_LIBRA && (LIBRA_CHIP_CS))

◆ CHIP_LIBRA_FPGA

#define CHIP_LIBRA_FPGA (CHIP_LIBRA && (LIBRA_CHIP_FPGA))

◆ CHIP_SOCMN1

#define CHIP_SOCMN1 (TARGET_CHIP_SOCMN1)

◆ CHIP_SOCMN1_ASIC

#define CHIP_SOCMN1_ASIC (CHIP_SOCMN1_V100 || CHIP_SOCMN1_V200)

◆ CHIP_SOCMN1_FPGA

#define CHIP_SOCMN1_FPGA (CHIP_SOCMN1 && (SOCMN1_CHIP_FPGA))

◆ CHIP_SOCMN1_V100

#define CHIP_SOCMN1_V100 (CHIP_SOCMN1 && (SOCMN1_CHIP_V100))

◆ CHIP_SOCMN1_V200

#define CHIP_SOCMN1_V200 (CHIP_SOCMN1 && (SOCMN1_CHIP_V200))

◆ CHIP_SW21

#define CHIP_SW21 (TARGET_CHIP_SW21)

◆ CHIP_SW21_ASIC

#define CHIP_SW21_ASIC (CHIP_SW21_V100)

◆ CHIP_SW21_FPGA

#define CHIP_SW21_FPGA (CHIP_SW21 && (SW21_CHIP_FPGA))

◆ CHIP_SW21_V100

#define CHIP_SW21_V100 (CHIP_SW21 && (SW21_CHIP_V100))

◆ CHIP_SW39

#define CHIP_SW39 (TARGET_CHIP_SW39)

◆ CHIP_SW39_FPGA

#define CHIP_SW39_FPGA (CHIP_SW39 && (SW39_CHIP_FPGA))

◆ CHIP_WS53_ASIC

#define CHIP_WS53_ASIC (CHIP_WS53_V100)

◆ CHIP_WS53_FPGA

#define CHIP_WS53_FPGA (CHIP_WS53 && (FPGA))

◆ CHIP_WS53_V100

#define CHIP_WS53_V100 (CHIP_WS53 && (ASIC))

◆ CHIP_WS63_ASIC

#define CHIP_WS63_ASIC (CHIP_WS63_V100)

◆ CHIP_WS63_FPGA

#define CHIP_WS63_FPGA (CHIP_WS63 && (FPGA))

◆ CHIP_WS63_V100

#define CHIP_WS63_V100 (CHIP_WS63 && (ASIC))

◆ CM3

#define CM3 0

◆ CM7

#define CM7 1

◆ CONTROL_CORE

#define CONTROL_CORE 6

◆ CORE_NUMS

#define CORE_NUMS 1

◆ CPU_NUM

#define CPU_NUM 1

◆ GNSS

#define GNSS 3

◆ HIFI

#define HIFI PROTOCOL

◆ MASTER_BY_ALL

#define MASTER_BY_ALL APPS

◆ MASTER_BY_BRANDY_ONLY

#define MASTER_BY_BRANDY_ONLY (CHIP_BRANDY && (CORE == APPS))

◆ MASTER_BY_BS20_ONLY

#define MASTER_BY_BS20_ONLY (CHIP_BS20 && (CORE == APPS))

◆ MASTER_BY_BS21_ONLY

#define MASTER_BY_BS21_ONLY (CHIP_BS21 && (CORE == APPS))

◆ MASTER_BY_BS21A_ONLY

#define MASTER_BY_BS21A_ONLY (CHIP_BS21A && (CORE == APPS))

◆ MASTER_BY_BS21E_ONLY

#define MASTER_BY_BS21E_ONLY (CHIP_BS21E && (CORE == APPS))

◆ MASTER_BY_BS22_ONLY

#define MASTER_BY_BS22_ONLY (CHIP_BS22 && (CORE == APPS))

◆ MASTER_BY_BS25_ONLY

#define MASTER_BY_BS25_ONLY (CHIP_BS25 && (CORE == APPS))

◆ MASTER_BY_BS26_ONLY

#define MASTER_BY_BS26_ONLY (CHIP_BS26 && (CORE == APPS))

◆ MASTER_BY_LIBRA_ONLY

#define MASTER_BY_LIBRA_ONLY (CHIP_LIBRA && (CORE == APPS))

◆ MASTER_BY_SOCMN1_ONLY

#define MASTER_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == APPS))

◆ MASTER_BY_SW21_ONLY

#define MASTER_BY_SW21_ONLY (CHIP_SW21 && (CORE == APPS))

◆ MASTER_BY_SW39_ONLY

#define MASTER_BY_SW39_ONLY (CHIP_SW39 && (CORE == APPS))

◆ MASTER_BY_WS53_ONLY

#define MASTER_BY_WS53_ONLY (CHIP_WS53 && (CORE == APPS))

◆ MASTER_ONLY

#define MASTER_ONLY

值:

                                     (MASTER_BY_LIBRA_ONLY || \
                                     MASTER_BY_SOCMN1_ONLY || MASTER_BY_BS25_ONLY || \
                                     MASTER_BY_BRANDY_ONLY || MASTER_BY_BS20_ONLY || \
                                     MASTER_BY_BS21_ONLY || MASTER_BY_BS21A_ONLY || \
                                     MASTER_BY_BS22_ONLY || MASTER_BY_BS26_ONLY || \
                                     MASTER_BY_WS53_ONLY || MASTER_BY_SW39_ONLY || \
                                     MASTER_BY_SW21_ONLY || MASTER_BY_BS21E_ONLY)

◆ MCU_ONLY

#define MCU_ONLY

值:

                                     (MASTER_BY_LIBRA_ONLY || MASTER_BY_SOCMN1_ONLY || \
                                     MASTER_BY_BS25_ONLY || MASTER_BY_BRANDY_ONLY || \
                                     MASTER_BY_WS53_ONLY || CHIP_WS63 || CHIP_BS20 || CHIP_BS21 || CHIP_BS21E || \
                                     CHIP_BS21A || CHIP_BS22 || CHIP_BS26 || MASTER_BY_SW39_ONLY || \
                                     MASTER_BY_SW21_ONLY)

◆ OTHER_CPU_NUM

#define OTHER_CPU_NUM (CPU_NUM - 1)

◆ PROTOCOL

#define PROTOCOL 1

◆ RISCV31

#define RISCV31 2

◆ RISCV32

#define RISCV32 4

◆ RISCV70

#define RISCV70 3

◆ SECURITY

#define SECURITY 4

◆ SENSOR

#define SENSOR 7

◆ SLAVE_BY_BRANDY_BT

#define SLAVE_BY_BRANDY_BT (CHIP_BRANDY && (CORE == BT))

◆ SLAVE_BY_BRANDY_DSP

#define SLAVE_BY_BRANDY_DSP (CHIP_BRANDY && (CORE == DSP))

◆ SLAVE_BY_BRANDY_ONLY

#define SLAVE_BY_BRANDY_ONLY (SLAVE_BY_BRANDY_BT || SLAVE_BY_BRANDY_DSP)

◆ SLAVE_BY_BS25_ONLY

#define SLAVE_BY_BS25_ONLY (CHIP_BS25 && (CORE == BT))

◆ SLAVE_BY_LIBRA_BT

#define SLAVE_BY_LIBRA_BT (CHIP_LIBRA && (CORE == BT))

◆ SLAVE_BY_LIBRA_GNSS

#define SLAVE_BY_LIBRA_GNSS (CHIP_LIBRA && (CORE == GNSS))

◆ SLAVE_BY_LIBRA_ONLY

#define SLAVE_BY_LIBRA_ONLY (SLAVE_BY_LIBRA_BT || SLAVE_BY_LIBRA_GNSS || SLAVE_BY_LIBRA_SECURITY)

◆ SLAVE_BY_LIBRA_SECURITY

#define SLAVE_BY_LIBRA_SECURITY (CHIP_LIBRA && (CORE == SECURITY))

◆ SLAVE_BY_SOCMN1_ONLY

#define SLAVE_BY_SOCMN1_ONLY (CHIP_SOCMN1 && (CORE == BT))

◆ SLAVE_BY_SW39_BT

#define SLAVE_BY_SW39_BT (CHIP_SW39 && (CORE == BT))

◆ SLAVE_BY_WS53_ONLY

#define SLAVE_BY_WS53_ONLY (CHIP_WS53 && (CORE == CONTROL_CORE))

◆ WIFI

#define WIFI 5