25#define RISCV_SYS_VECTOR_CNT 26
26#define HH503_MAC_RPT_INTR_RX_TRIG_FRM_MASK 0x40000000
27#define HH503_MAC_RPT_INTR_RX_NORM_COMPLETE_MASK 0x1
28#define HH503_MAC_RPT_INTR_RX_HIPRI_COMPLETE_MASK 0x4
29#define HH503_MAC_RPT_INTR_TX_COMPLETE_MASK 0x2
30#define HH503_MAC_RPT_INTR_VAP0_TBTT_MASK 0x100
31#define HH503_MAC_RPT_INTR_VAP1_TBTT_MASK 0x80
32#define HH503_MAC_RPT_INTR_VAP2_TBTT_MASK 0x40
33#define HH503_MAC_RPT_INTR_ERROR_MASK 0x8
34#define HH503_MAC_RPT_INTR_CH_STATISTIC_DONE_MASK 0x20000
35#define HH503_MAC_RPT_INTR_ONE_PACKET_DONE_MASK 0x4000
36#define HH503_MAC_RPT_INTR_CSI_DONE_MASK 0x2000
37#define HH503_MAC_RPT_INTR_P2P_CT_WINDOW_END_MASK 0x40000
38#define HH503_MAC_RPT_INTR_P2P_NOA_ABSENT_START_MASK 0x80000
39#define HH503_MAC_RPT_INTR_P2P_NOA_ABSENT_END_MASK 0x100000
40#define HH503_MAC_RPT_INTR_VAP0_WAIT_BCN_TIMEOUT_MASK 0x200000
41#define HH503_MAC_RPT_INTR_VAP1_WAIT_BCN_TIMEOUT_MASK 0x400000
42#define HH503_MAC_RPT_INTR_VAP2_WAIT_BCN_TIMEOUT_MASK 0x800000
43#define HH503_MAC_RPT_INTR_ABORT_START_MASK 0x200
44#define HH503_MAC_RPT_INTR_ABORT_DONE_MASK 0x8000
45#define HH503_MAC_RPT_INTR_MODE_SELECT_END_MASK 0x10000
46#define HH503_MAC_RPT_INTR_ABORT_END_MASK 0x400
47#define HH503_MAC_RPT_INTR_FTM_MASK 0x10000000
48#define HH503_MAC_RPT_INTR_HE_ROM_UPDATE_MASK 0x80000000
49#define HH503_MAC_RPT_INTR_BCN_NO_FRM_MASK 0x20000000
50#define HH503_MAC_IS_TRS_OFFSET 8
51#define HH503_MAC_IS_TRS_MASK 0x100
52#define HH503_MAC_TRIG_AP_TX_POWER_LSB_OFFSET 28
53#define HH503_MAC_TRIG_AP_TX_POWER_LSB_MASK 0xF0000000
54#define HH503_MAC_TRIG_AP_TX_POWER_MSB_OFFSET 0
55#define HH503_MAC_TRIG_AP_TX_POWER_MSB_MASK 0x3
56#define HH503_MAC_TRIG_TYPE_OFFSET 0
57#define HH503_MAC_TRIG_TYPE_MASK 0xF
58#define HH503_MAC_TRIG_UL_BW_OFFSET 18
59#define HH503_MAC_TRIG_UL_BW_MASK 0xC0000
61#define NUM_HAL_INTERRUPT_WLAN (19 + RISCV_SYS_VECTOR_CNT)
62#define NUM_HAL_INTERRUPT_PHY (18 + RISCV_SYS_VECTOR_CNT)
63#define IRQ_FLAG_PRI8 8
64#define IRQ_FLAG_PRI11 11
65#define HH503_MAC0_IRQ NUM_HAL_INTERRUPT_WLAN
66#define HH503_PHY0_IRQ NUM_HAL_INTERRUPT_PHY
osal_void(* hh503_cb_irq_mac_isr)(u_interrupt_status *status)
Definition hal_irq_rom.h:76
osal_void(* hh503_cb_irq_phy_isr)(u_interrupt_status *status)
Definition hal_irq_rom.h:77
osal_u32(* hal_p2p_noa_absent_end)(hal_device_stru *hal_device, osal_u8 data)
Definition hal_irq_rom.h:86
osal_void hal_mask_interrupt(osal_u32 offset)
osal_u32(* hal_p2p_noa_absent_start)(hal_device_stru *hal_device, osal_u8 data)
Definition hal_irq_rom.h:87
osal_s32 hh503_irq_phy_all(osal_s32 p1, osal_void *p2)
osal_s32 hh503_irq_isr_all(osal_s32 p1, osal_void *p2)
osal_void hh503_irq_mac_isr_cb(u_interrupt_status *status)
osal_void hh503_clear_mac_error_int_status(const hal_error_state_stru *status)
osal_void hh503_irq_rx_txbf_frame_process(hal_to_dmac_device_stru *hal_device, osal_u32 *base_dscr, osal_u8 queue_id)
osal_void hal_set_noa_count(osal_u16 value)
int osal_s32
Definition osal_types.h:19
unsigned char osal_u8
Definition osal_types.h:11
void osal_void
Definition osal_types.h:29
unsigned int osal_u32
Definition osal_types.h:13
unsigned short osal_u16
Definition osal_types.h:12
Definition hal_common_ops_device_rom.h:1190
Definition hal_device_rom.h:39
Definition hal_ops_common_rom.h:529
Definition hal_uart_v151_regs_def.h:38