hal_dma.h

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#ifndef HAL_DMA_H
#define HAL_DMA_H
 
#include <stdint.h>
#include <stdbool.h>
#include "common_def.h"
#include "errcode.h"
#include "dma_porting.h"
 
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cplusplus */
#endif /* __cplusplus */
typedef void (*hal_dma_transfer_cb_t)(uint8_t intr, uint8_t channel, uintptr_t arg);
 
typedef enum hal_dma_data_width {
    HAL_DMA_TRANSFER_WIDTH_8,
    HAL_DMA_TRANSFER_WIDTH_16,
    HAL_DMA_TRANSFER_WIDTH_32,
    HAL_DMA_TRANSFER_WIDTH_64,
    HAL_DMA_TRANSFER_WIDTH_128,
    HAL_DMA_TRANSFER_WIDTH_256
} hal_dma_data_width_t;
 
typedef enum hal_dma_burst_transaction_length {
    HAL_DMA_BURST_TRANSACTION_LENGTH_1,
    HAL_DMA_BURST_TRANSACTION_LENGTH_4,
    HAL_DMA_BURST_TRANSACTION_LENGTH_8,
    HAL_DMA_BURST_TRANSACTION_LENGTH_16,
    HAL_DMA_BURST_TRANSACTION_LENGTH_32,
    HAL_DMA_BURST_TRANSACTION_LENGTH_64,
    HAL_DMA_BURST_TRANSACTION_LENGTH_128,
    HAL_DMA_BURST_TRANSACTION_LENGTH_256
} hal_dma_burst_transaction_length_t;
 
typedef enum hal_dma_address_inc {
    HAL_DMA_ADDRESS_INC_INCREMENT,
    HAL_DMA_ADDRESS_INC_DECREMENT,
    HAL_DMA_ADDRESS_INC_NO_CHANGE,
    HAL_DMA_ADDRESS_INC_TYPES
} hal_dma_address_inc_t;
 
typedef enum hal_dma_ch_priority {
    HAL_DMA_CH_PRIORITY_0,
    HAL_DMA_CH_PRIORITY_1,
    HAL_DMA_CH_PRIORITY_2,
    HAL_DMA_CH_PRIORITY_3
} hal_dma_ch_priority_t;
 
typedef enum hal_dma_trans_type {
    HAL_DMA_TRANS_MEMORY_TO_MEMORY_DMA,
    HAL_DMA_TRANS_MEMORY_TO_PERIPHERAL_DMA,
    HAL_DMA_TRANS_PERIPHERAL_TO_MEMORY_DMA,
    HAL_DMA_TRANS_PERIPHERAL_TO_PERIPHERAL_DMA,
    HAL_DMA_TRANS_PERIPHERAL_TO_MEMORY_PERIPHERAL,
    HAL_DMA_TRANS_PERIPHERAL_TO_PERIPHERAL_SRC,
    HAL_DMA_TRANS_MEMORY_TO_PERIPHERAL_PERIPHERAL,
    HAL_DMA_TRANS_PERIPHERAL_TO_PERIPHERAL_DST
} hal_dma_trans_type_t;
 
typedef enum hal_dma_protection_control {
    HAL_DMA_PROTECTION_CONTROL_NONE,
    HAL_DMA_PROTECTION_CONTROL_PRIVILEGED,
    HAL_DMA_PROTECTION_CONTROL_BUFFERABLE,
    HAL_DMA_PROTECTION_CONTROL_PRIVILEGED_BUFFERABLE,
    HAL_DMA_PROTECTION_CONTROL_CACHEABLE,
    HAL_DMA_PROTECTION_CONTROL_PRIVILEGED_CACHEABLE,
    HAL_DMA_PROTECTION_CONTROL_BUFFERABLE_CACHEABLE,
    HAL_DMA_PROTECTION_CONTROL_ALL
} hal_dma_protection_control_t;
 
typedef enum hal_dma_mux_handshaking_status {
    HAL_DMA_MUX_HANDSHAKING_IDLE,
    HAL_DMA_MUX_HANDSHAKING_USING
} hal_dma_mux_handshaking_status_t;
 
typedef enum dma_ch_transfer_dir {
    HAL_DMA_TRANSFER_DIR_MEM_TO_PERIPHERAL,
    HAL_DMA_TRANSFER_DIR_PERIPHERAL_TO_MEM,
    HAL_DMA_TRANSFER_DIR_PERIPHERAL_TO_PERIPHERAL
} dma_ch_transfer_dir_t;
 
typedef enum hal_dma_handshaking_select {
    HAL_DMA_HARDWARE_HANDSHAKING = 0x0,
    HAL_DMA_SOFTWARE_HANDSHAKING = 0x1
} hal_dma_handshaking_select_t;
 
typedef enum hal_dma_interrupt {
    HAL_DMA_INTERRUPT_TFR,
    HAL_DMA_INTERRUPT_BLOCK,
    HAL_DMA_INTERRUPT_SRCTRAN,
    HAL_DMA_INTERRUPT_DSTTRAN,
    HAL_DMA_INTERRUPT_ERR
} hal_dma_interrupt_t;
 
typedef enum hal_dma_master_select {
    HAL_DMA_MASTER_SELECT_DEFAULT = 0x0,
    HAL_DMA_MASTER_SELECT_0 = 0x0,
    HAL_DMA_MASTER_SELECT_1 = 0x1,
    HAL_DMA_MASTER_SELECT_2 = 0x2,
    HAL_DMA_MASTER_SELECT_3 = 0x3,
    HAL_DMA_MASTER_SELECT_HIGHEST = 0x3,
    HAL_DMA_MASTER_SELECT_ERROR = 0x4
} hal_dma_master_select_t;
 
typedef enum hal_dma_ch_state {
    HAL_DMA_CH_STATE_CLOSED,
    HAL_DMA_CH_STATE_IDLE,
    HAL_DMA_CH_STATE_ACTIVE,
    HAL_DMA_CH_STATE_ERROR
} hal_dma_ch_state_t;
 
typedef struct hal_dma_transfer_base_config {
    uint32_t src;
    uint32_t dest;
    uint16_t transfer_num;
    hal_dma_ch_priority_t priority;
    hal_dma_data_width_t src_width;
    hal_dma_data_width_t dest_width;
    hal_dma_address_inc_t src_inc;
    hal_dma_address_inc_t dest_inc;
    hal_dma_burst_transaction_length_t src_burst_trans_length;
    hal_dma_burst_transaction_length_t dest_burst_trans_length;
    hal_dma_transfer_cb_t callback;
    uintptr_t priv_arg;
} hal_dma_transfer_base_config_t;
 
typedef struct hal_dma_transfer_peri_config {
    hal_dma_trans_type_t trans_type;
    dma_ch_transfer_dir_t trans_dir;
    hal_dma_handshaking_source_t hs_source;
    hal_dma_handshaking_source_t hs_dest;
    hal_dma_protection_control_t protection;
} hal_dma_transfer_peri_config_t;
 
typedef enum hal_dma_type {
    HAL_DMA_TYPE_BDMA,
    HAL_DMA_TYPE_SDMA
} hal_dma_type_t;
 
errcode_t hal_dma_init(void);
 
void hal_dma_deinit(void);
 
void hal_dma_open(void);
 
void hal_dma_close(void);
 
void hal_dma_enable(dma_channel_t ch, bool en);
 
uint32_t hal_dma_get_block(dma_channel_t ch);
 
void hal_dma_interrupt_clear(dma_channel_t ch, hal_dma_interrupt_t int_type);
 
dma_channel_t hal_dma_get_idle_ch(hal_dma_handshaking_source_t source,
                                  hal_dma_burst_transaction_length_t burst_length);
 
errcode_t hal_dma_config_single_block(dma_channel_t ch,
                                      const hal_dma_transfer_base_config_t *base_cfg,
                                      hal_dma_transfer_peri_config_t *periph_cfg);
 
errcode_t hal_dma_add_lli_transfer(dma_channel_t ch,
                                   const hal_dma_transfer_base_config_t *base_cfg,
                                   hal_dma_transfer_peri_config_t *periph_cfg);
 
bool hal_dma_is_enabled(dma_channel_t ch);
 
void hal_dma_enable_lli(dma_channel_t ch, hal_dma_transfer_cb_t callback, uintptr_t arg);
 
errcode_t dma_port_set_mux_channel(dma_channel_t ch, hal_dma_transfer_peri_config_t *per_cfg);
 
void dma_port_set_channel_handshaking_source(hal_dma_hardshaking_channel_t ch, hal_dma_handshaking_source_t source);
 
hal_dma_master_select_t dma_port_get_master_select(dma_channel_t ch, uint32_t addr);
 
errcode_t hal_dma_regs_init(void);
 
#if defined (CONFIG_DMA_SUPPORT_LPM)
errcode_t hal_dma_suspend(uintptr_t arg);
 
errcode_t hal_dma_resume(uintptr_t arg);
#endif
 
#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cplusplus */
#endif /* __cplusplus */
 
#endif