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riscv_interrupt.h
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1/* ----------------------------------------------------------------------------
2 * Copyright (c) Huawei Technologies Co., Ltd. 2021-2021. All rights reserved.
3 * Description: Riscv Himideerv200 Interrupt Register HeadFile
4 * Author: Huawei LiteOS Team
5 * Create: 2021-02-02
6 * Redistribution and use in source and binary forms, with or without modification,
7 * are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice, this list of
9 * conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice, this list
11 * of conditions and the following disclaimer in the documentation and/or other materials
12 * provided with the distribution.
13 * 3. Neither the name of the copyright holder nor the names of its contributors may be used
14 * to endorse or promote products derived from this software without specific prior written
15 * permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * --------------------------------------------------------------------------- */
28
29/* ----------------------------------------------------------------------------
30 * This file has been modified in accordance with Misra-C specifications.
31 * ---------------------------------------------------------------------------- */
32#ifndef RISCV_INTERRUPT_H
33#define RISCV_INTERRUPT_H
34
35#ifdef __cplusplus
36extern "C" {
37#endif /* __cplusplus */
38
39/* local interrupt Register */
40#define LOCIPRI0 0xBC0
41#define LOCIPRI1 0xBC1
42#define LOCIPRI2 0xBC2
43#define LOCIPRI3 0xBC3
44#define LOCIPRI4 0xBC4
45#define LOCIPRI5 0xBC5
46#define LOCIPRI6 0xBC6
47#define LOCIPRI7 0xBC7
48#define LOCIPRI8 0xBC8
49#define LOCIPRI9 0xBC9
50#define LOCIPRI10 0xBCA
51#define LOCIPRI11 0xBCB
52#define LOCIPRI12 0xBCC
53#define LOCIPRI13 0xBCD
54#define LOCIPRI14 0xBCE
55#define LOCIPRI15 0xBCF
56
57#define LOCIEN0 0xBE0
58#define LOCIEN1 0xBE1
59#define LOCIEN2 0xBE2
60#define LOCIEN3 0xBE3
61#define LOCIPD0 0xBE8
62#define LOCIPD1 0xBE9
63#define LOCIPD2 0xBEA
64#define LOCIPD3 0xBEB
65#define LOCIPD4 0xBEC
66#define LOCIPD5 0xBED
67#define LOCIPD6 0xBEE
68
69#define LOCIPRI_REG0 0
70#define LOCIPRI_REG1 1
71#define LOCIPRI_REG2 2
72#define LOCIPRI_REG3 3
73#define LOCIPRI_REG4 4
74#define LOCIPRI_REG5 5
75#define LOCIPRI_REG6 6
76#define LOCIPRI_REG7 7
77#define LOCIPRI_REG8 8
78#define LOCIPRI_REG9 9
79#define LOCIPRI_REG10 10
80#define LOCIPRI_REG11 11
81#define LOCIPRI_REG12 12
82#define LOCIPRI_REG13 13
83#define LOCIPRI_REG14 14
84#define LOCIPRI_REG15 15
85
86#define LOCIEN_REG0 0
87#define LOCIEN_REG1 1
88#define LOCIEN_REG2 2
89#define LOCIEN_REG3 3
90#define LOCIEN_REG4 4
91
92#define LOCIPD_REG0 0
93#define LOCIPD_REG1 1
94#define LOCIPD_REG2 2
95#define LOCIPD_REG3 3
96#define LOCIPD_REG4 4
97#define LOCIPD_REG5 5
98#define LOCIPD_REG6 6
99
100/* local interrupt pending clear register */
101#define LOCIPCLR 0xBF0
102
103#ifdef __cplusplus
104}
105#endif /* __cplusplus */
106
107#endif /* RISCV_INTERRUPT_H */