d6/dbf/osal__barrier_8h_source.html

/*

 * Copyright (c) HiSilicon (Shanghai) Technologies Co., Ltd. 2021-2022. All rights reserved.

 * Description: OS Abstract Layer.

 */


#ifndef __OSAL_BARRIER_H__

#define __OSAL_BARRIER_H__


#ifdef __cplusplus

#if __cplusplus

extern "C" {

#endif

#endif


void osal_mb(void);


void osal_rmb(void);


void osal_wmb(void);


void osal_smp_mb(void);


void osal_smp_rmb(void);


void osal_smp_wmb(void);


void osal_isb(void);


void osal_dsb(void);


void osal_dmb(void);


#ifdef __cplusplus

#if __cplusplus

}

#endif

#endif

#endif /* __OSAL_BARRIER_H__ */

osal_isb
void osal_isb(void)
Instruction Synchronization Barrier.
Definition osal_barrier.c:29

osal_smp_mb
void osal_smp_mb(void)
General basic CPU memory barriers, SMP conditional.
Definition osal_barrier.c:20

osal_dsb
void osal_dsb(void)
Data Synchronization Barrier.
Definition osal_barrier.c:37

osal_rmb
void osal_rmb(void)
Read basic CPU memory barriers
Definition osal_barrier.c:14

osal_mb
void osal_mb(void)
General basic CPU memory barriers
Definition osal_barrier.c:11

osal_smp_wmb
void osal_smp_wmb(void)
Write basic CPU memory barriers, SMP conditional.
Definition osal_barrier.c:26

osal_dmb
void osal_dmb(void)
Data Memory Barrier.
Definition osal_barrier.c:45

osal_wmb
void osal_wmb(void)
Write basic CPU memory barriers
Definition osal_barrier.c:17

osal_smp_rmb
void osal_smp_rmb(void)
Read basic CPU memory barriers, SMP conditional.
Definition osal_barrier.c:23